+---------------------------------------------------------------------+
|  Log file: mau.log                                                  |
|  Compiler version: 5.1.0 (fca32d1)                                  |
|  Created on: Fri Sep  8 08:24:30 2017                               |
+---------------------------------------------------------------------+

Match Table table0 did not specify the number of entries required. A default value (512) will be used.
Match Entry Table table0 has already been associated with stat Table table0_counter.
Cannot implement table0 in phase 0 resources because table uses side effect tables.
Match Table table0 did not specify the number of entries required. A default value (512) will be used.
Match Entry Table table0 has already been associated with stat Table table0_counter.
Cannot implement table0 in phase 0 resources because table uses side effect tables.
Match Table table0 did not specify the number of entries required. A default value (512) will be used.
POV/metadata bridge containers added between ingress/egress: [0]
Metadata bridge_ingress_intrinsic containers added between ingress/egress: [128]
Match Entry Table table0 has already been associated with stat Table table0_counter.
Match table ingress_port_count_table has no match key fields
Cannot use hash-action for table ingress_port_count_table with no key because the number of entries required by side-effect table ingress_port_counter is not a power of 2 -- 510.

##########################################
  Call to decide_action_data_placement(stage=0, table=ingress_port_count_table)
##########################################


Max immediate bits used in any action is 0 bits.
Overhead bit width for table ingress_port_count_table is 22 bits.
Bits available in overhead for non-essential immediate data is 32 bits.
~~~~~~~~~~~~~~~~~~~~~
 Examining placing 0 bits in match overhead
Overhead bit width for table ingress_port_count_table is 22 bits.
Overhead SRAMs to use = 97
  Entries requested = 1024  and match entries get = 0
ram_size_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0

immediate_size_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0

hash_to_phv_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0

total action ram packing size = [0, 0, 0]
action_ram_packing:
  action count_ingress has []
total action ram packing size = [0, 0, 0]
action_ram_packing:
  action count_ingress has []
total action ram packing size = [0, 0, 0]
action_ram_packing:
  action count_ingress has []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
Action Data SRAMs to use = 0
TODO: Total RAMs use when put 0 bits in match overhead: 97
TODO: Total RAMs use when put 0 bits in match overhead: 97
~~~~~~~~~~~~~~~~~~~~~
 Examining placing 8 bits in match overhead
~~~~~~~~~~~~~~~~~~~~~
 Examining placing 16 bits in match overhead
~~~~~~~~~~~~~~~~~~~~~
 Examining placing 24 bits in match overhead
~~~~~~~~~~~~~~~~~~~~~
 Examining placing 32 bits in match overhead

##########################################

Best Ram Usage is 97 rams
Best Immediate placement is 0 bits
Match table egress_port_count_table has no match key fields
Cannot use hash-action for table egress_port_count_table with no key because the number of entries required by side-effect table egress_port_counter is not a power of 2 -- 510.

##########################################
  Call to decide_action_data_placement(stage=0, table=egress_port_count_table)
##########################################


Max immediate bits used in any action is 0 bits.
Overhead bit width for table egress_port_count_table is 20 bits.
Bits available in overhead for non-essential immediate data is 32 bits.
~~~~~~~~~~~~~~~~~~~~~
 Examining placing 0 bits in match overhead
Overhead bit width for table egress_port_count_table is 20 bits.
Overhead SRAMs to use = 97
  Entries requested = 1024  and match entries get = 0
ram_size_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0

immediate_size_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0

hash_to_phv_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0

total action ram packing size = [0, 0, 0]
action_ram_packing:
  action count_egress has []
total action ram packing size = [0, 0, 0]
action_ram_packing:
  action count_egress has []
total action ram packing size = [0, 0, 0]
action_ram_packing:
  action count_egress has []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
Action Data SRAMs to use = 0
TODO: Total RAMs use when put 0 bits in match overhead: 97
TODO: Total RAMs use when put 0 bits in match overhead: 97
~~~~~~~~~~~~~~~~~~~~~
 Examining placing 8 bits in match overhead
~~~~~~~~~~~~~~~~~~~~~
 Examining placing 16 bits in match overhead
~~~~~~~~~~~~~~~~~~~~~
 Examining placing 24 bits in match overhead
~~~~~~~~~~~~~~~~~~~~~
 Examining placing 32 bits in match overhead

##########################################

Best Ram Usage is 97 rams
Best Immediate placement is 0 bits

##########################################
  Call to decide_action_data_placement(stage=0, table=process_packet_out_table)
##########################################


Max immediate bits used in any action is 0 bits.
Overhead bit width for table process_packet_out_table is 0 bits.
Bits available in overhead for non-essential immediate data is 32 bits.
~~~~~~~~~~~~~~~~~~~~~
 Examining placing 0 bits in match overhead
Overhead bit width for table process_packet_out_table is 0 bits.
Overhead SRAMs to use = 97
  Entries requested = 1024  and match entries get = 0
ram_size_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0

immediate_size_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0

hash_to_phv_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0

total action ram packing size = [0, 0, 0]
action_ram_packing:
  action _process_packet_out has []
total action ram packing size = [0, 0, 0]
action_ram_packing:
  action _process_packet_out has []
total action ram packing size = [0, 0, 0]
action_ram_packing:
  action _process_packet_out has []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
Action Data SRAMs to use = 0
TODO: Total RAMs use when put 0 bits in match overhead: 97
TODO: Total RAMs use when put 0 bits in match overhead: 97
~~~~~~~~~~~~~~~~~~~~~
 Examining placing 8 bits in match overhead
~~~~~~~~~~~~~~~~~~~~~
 Examining placing 16 bits in match overhead
~~~~~~~~~~~~~~~~~~~~~
 Examining placing 24 bits in match overhead
~~~~~~~~~~~~~~~~~~~~~
 Examining placing 32 bits in match overhead

##########################################

Best Ram Usage is 97 rams
Best Immediate placement is 0 bits

##########################################
  Call to decide_action_data_placement(stage=0, table=table0)
##########################################


Max immediate bits used in any action is 0 bits.
Overhead bit width for table table0 is 3 bits.
Bits available in overhead for non-essential immediate data is 32 bits.
~~~~~~~~~~~~~~~~~~~~~
 Examining placing 0 bits in match overhead
Overhead bit width for table table0 is 3 bits.
Overhead SRAMs to use = 1
  Entries requested = 512  and match entries get = 512
ram_size_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               1                0               0                0                0        # 0
       0              0              0               1                0               0                0                0        # 1
       0              0              0               0                0               0                0                0        # 2

immediate_size_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0
       0              0              0               0                0               0                0                0        # 1
       0              0              0               0                0               0                0                0        # 2

hash_to_phv_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0
       0              0              0               0                0               0                0                0        # 1
       0              0              0               0                0               0                0                0        # 2

total action ram packing size = [16, 0, 0]
action_ram_packing:
  action set_egress_port has [(16, 16, False)]
  action send_to_cpu has [(16, 16, False)]
  action _drop has []
total action ram packing size = [16, 0, 0]
action_ram_packing:
  action set_egress_port has []
  action send_to_cpu has []
  action _drop has []
total action ram packing size = [16, 0, 0]
action_ram_packing:
  action set_egress_port has []
  action send_to_cpu has []
  action _drop has []
byte_enables = [1, 1]
Allocating Action Parameter Bus Byte 32 in stage 0 for Byte 0 of 16-bit constant
Allocating Action Parameter Bus Byte 33 in stage 0 for Byte 1 of 16-bit constant
Allocating Action Parameter Bus Byte 34 in stage 0 for Byte 0 of 16-bit constant
Allocating Action Parameter Bus Byte 35 in stage 0 for Byte 1 of 16-bit constant
After allocation of 32s, available_slots is [(16, 0, 0), (32, 8, 0), (16, 1, 16)]
final packing is [(16, 16, False)]
final packing is [(16, 16, False)]
final packing is []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
final packing is []
final packing is []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
final packing is []
final packing is []
Action Data SRAMs to use = 1
TODO: Total RAMs use when put 0 bits in match overhead: 2
TODO: Total RAMs use when put 0 bits in match overhead: 2
~~~~~~~~~~~~~~~~~~~~~
 Examining placing 8 bits in match overhead
~~~~~~~~~~~~~~~~~~~~~
 Examining placing 16 bits in match overhead
Overhead bit width for table table0 is 3 bits.
Overhead SRAMs to use = 1
  Entries requested = 512  and match entries get = 512
ram_size_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0
       0              0              0               0                0               0                0                0        # 1
       0              0              0               0                0               0                0                0        # 2

immediate_size_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               1                0               0                0                0        # 0
       0              0              0               1                0               0                0                0        # 1
       0              0              0               0                0               0                0                0        # 2

hash_to_phv_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0
       0              0              0               0                0               0                0                0        # 1
       0              0              0               0                0               0                0                0        # 2

total action ram packing size = [0, 0, 0]
action_ram_packing:
  action set_egress_port has []
  action send_to_cpu has []
  action _drop has []
total action ram packing size = [0, 16, 0]
action_ram_packing:
  action set_egress_port has [(16, 16, False)]
  action send_to_cpu has [(16, 16, False)]
  action _drop has []
total action ram packing size = [0, 16, 0]
action_ram_packing:
  action set_egress_port has []
  action send_to_cpu has []
  action _drop has []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
final packing is []
final packing is []
byte_enables = [1, 1]
Allocating Action Parameter Bus Byte 32 in stage 0 for Byte 0 of 16-bit constant
Allocating Action Parameter Bus Byte 33 in stage 0 for Byte 1 of 16-bit constant
Allocating Action Parameter Bus Byte 34 in stage 0 for Byte 0 of 16-bit constant
Allocating Action Parameter Bus Byte 35 in stage 0 for Byte 1 of 16-bit constant
After allocation of 32s, available_slots is [(16, 0, 0), (32, 8, 0), (16, 1, 16)]
final packing is [(16, 16, False)]
final packing is [(16, 16, False)]
final packing is []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
final packing is []
final packing is []
Action Data SRAMs to use = 0
TODO: Total RAMs use when put 16 bits in match overhead: 1
TODO: Total RAMs use when put 16 bits in match overhead: 1
~~~~~~~~~~~~~~~~~~~~~
 Examining placing 24 bits in match overhead
Overhead bit width for table table0 is 3 bits.
Overhead SRAMs to use = 1
  Entries requested = 512  and match entries get = 512
ram_size_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0
       0              0              0               0                0               0                0                0        # 1
       0              0              0               0                0               0                0                0        # 2

immediate_size_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               1                0               0                0                0        # 0
       0              0              0               1                0               0                0                0        # 1
       0              0              0               0                0               0                0                0        # 2

hash_to_phv_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0
       0              0              0               0                0               0                0                0        # 1
       0              0              0               0                0               0                0                0        # 2

total action ram packing size = [0, 0, 0]
action_ram_packing:
  action set_egress_port has []
  action send_to_cpu has []
  action _drop has []
total action ram packing size = [0, 16, 0]
action_ram_packing:
  action set_egress_port has [(16, 16, False)]
  action send_to_cpu has [(16, 16, False)]
  action _drop has []
total action ram packing size = [0, 16, 0]
action_ram_packing:
  action set_egress_port has []
  action send_to_cpu has []
  action _drop has []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
final packing is []
final packing is []
byte_enables = [1, 1]
Allocating Action Parameter Bus Byte 32 in stage 0 for Byte 0 of 16-bit constant
Allocating Action Parameter Bus Byte 33 in stage 0 for Byte 1 of 16-bit constant
Allocating Action Parameter Bus Byte 34 in stage 0 for Byte 0 of 16-bit constant
Allocating Action Parameter Bus Byte 35 in stage 0 for Byte 1 of 16-bit constant
After allocation of 32s, available_slots is [(16, 0, 0), (32, 8, 0), (16, 1, 16)]
final packing is [(16, 16, False)]
final packing is [(16, 16, False)]
final packing is []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
final packing is []
final packing is []
Action Data SRAMs to use = 0
TODO: Total RAMs use when put 24 bits in match overhead: 1
TODO: Total RAMs use when put 24 bits in match overhead: 1
~~~~~~~~~~~~~~~~~~~~~
 Examining placing 32 bits in match overhead
Overhead bit width for table table0 is 3 bits.
Overhead SRAMs to use = 1
  Entries requested = 512  and match entries get = 512
ram_size_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0
       0              0              0               0                0               0                0                0        # 1
       0              0              0               0                0               0                0                0        # 2

immediate_size_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               1                0               0                0                0        # 0
       0              0              0               1                0               0                0                0        # 1
       0              0              0               0                0               0                0                0        # 2

hash_to_phv_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0
       0              0              0               0                0               0                0                0        # 1
       0              0              0               0                0               0                0                0        # 2

total action ram packing size = [0, 0, 0]
action_ram_packing:
  action set_egress_port has []
  action send_to_cpu has []
  action _drop has []
total action ram packing size = [0, 16, 0]
action_ram_packing:
  action set_egress_port has [(16, 16, False)]
  action send_to_cpu has [(16, 16, False)]
  action _drop has []
total action ram packing size = [0, 16, 0]
action_ram_packing:
  action set_egress_port has []
  action send_to_cpu has []
  action _drop has []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
final packing is []
final packing is []
byte_enables = [1, 1]
Allocating Action Parameter Bus Byte 32 in stage 0 for Byte 0 of 16-bit constant
Allocating Action Parameter Bus Byte 33 in stage 0 for Byte 1 of 16-bit constant
Allocating Action Parameter Bus Byte 34 in stage 0 for Byte 0 of 16-bit constant
Allocating Action Parameter Bus Byte 35 in stage 0 for Byte 1 of 16-bit constant
After allocation of 32s, available_slots is [(16, 0, 0), (32, 8, 0), (16, 1, 16)]
final packing is [(16, 16, False)]
final packing is [(16, 16, False)]
final packing is []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
final packing is []
final packing is []
Action Data SRAMs to use = 0
TODO: Total RAMs use when put 32 bits in match overhead: 1
TODO: Total RAMs use when put 32 bits in match overhead: 1

##########################################

Best Ram Usage is 1 rams
Best Immediate placement is 16 bits
Cannot implement table0 in phase 0 resources because table uses side effect tables.

----------------------------------------------
Call to Allocate P4 Table with table table0__action__, number_entries = 512, table id = None, and match type = exact
  Allocating in stage 0
----------------------------------------------

ram_size_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0
       0              0              0               0                0               0                0                0        # 1
       0              0              0               0                0               0                0                0        # 2

immediate_size_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               1                0               0                0                0        # 0
       0              0              0               1                0               0                0                0        # 1
       0              0              0               0                0               0                0                0        # 2

hash_to_phv_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0
       0              0              0               0                0               0                0                0        # 1
       0              0              0               0                0               0                0                0        # 2

total action ram packing size = [0, 0, 0]
action_ram_packing:
  action set_egress_port has []
  action send_to_cpu has []
  action _drop has []
total action ram packing size = [0, 16, 0]
action_ram_packing:
  action set_egress_port has [(16, 16, False)]
  action send_to_cpu has [(16, 16, False)]
  action _drop has []
total action ram packing size = [0, 16, 0]
action_ram_packing:
  action set_egress_port has []
  action send_to_cpu has []
  action _drop has []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
final packing is []
final packing is []
byte_enables = [1, 1]
Allocating Action Parameter Bus Byte 32 in stage 0 for Byte 0 of 16-bit constant
Allocating Action Parameter Bus Byte 33 in stage 0 for Byte 1 of 16-bit constant
Allocating Action Parameter Bus Byte 34 in stage 0 for Byte 0 of 16-bit constant
Allocating Action Parameter Bus Byte 35 in stage 0 for Byte 1 of 16-bit constant
After allocation of 32s, available_slots is [(16, 0, 0), (32, 8, 0), (16, 1, 16)]
final packing is [(16, 16, False)]
final packing is [(16, 16, False)]
final packing is []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
final packing is []
final packing is []
Allocating Action Logical Table ID 0 in stage 0

----------------------------------------------
Call to Allocate P4 Table with table table0_counter, number_entries = 512, table id = None, and match type = exact
  Allocating in stage 0
----------------------------------------------

stat_stage_table referenced: direct
stat Table Resource Request is:
SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams.
Sram Resource Request for P4 table table0_counter with handle 67108867 of type statistics in stage 0
  table_type : statistics
  rams_for_width : 1
  use_stash : False
  number_ways : 1
  way #0
  SRAM Request Group 0
      rams_for_depth : 2
      map_rams : 0
      way_number : 0
      ram_word_select_bits : 0
      ram_enable_select_bits : 0


----------------------------------------------
Call to Allocate P4 Table with table table0, number_entries = 512, table id = None, and match type = ternary
  Allocating in stage 0
----------------------------------------------

Logical Table ID in stage 0 was not supplied by table placement for table table0.
Allocating Logical Table ID 0 in stage 0
Allocating Table Type ID 0 of type ternary in stage 0

-----------------------------------------
 Call to allocate_ternary_match_key_2
-----------------------------------------
Total crossbar bytes to allocate = 16
Minimum key bytes required by this match key = 16
Allocating: Byte 133 is of type ternary and member of group 0 with 1 bytes
  version/valid in nibble 1 for table table0. for version/valid
{unused[6:0], ig_intr_md.ingress_port[8:8]}.
Allocating: Byte 128 is of type ternary and member of group 0 with 5 bytes. for {ethernet.srcAddr[7:0]}.
Allocating: Byte 129 is of type ternary and member of group 0 with 5 bytes. for {ethernet.srcAddr[15:8]}.
Allocating: Byte 130 is of type ternary and member of group 0 with 5 bytes. for {ethernet.srcAddr[23:16]}.
Allocating: Byte 131 is of type ternary and member of group 0 with 5 bytes. for {ethernet.srcAddr[31:24]}.
Allocating: Byte 132 is of type ternary and member of group 0 with 5 bytes. for {ethernet.dstAddr[15:8]}.
Allocating: Byte 134 is of type ternary and member of group 1 with 5 bytes. for {ethernet.dstAddr[31:24]}.
Allocating: Byte 135 is of type ternary and member of group 1 with 5 bytes. for {ethernet.dstAddr[39:32]}.
Allocating: Byte 136 is of type ternary and member of group 1 with 5 bytes. for {ethernet.etherType[7:0]}.
Allocating: Byte 137 is of type ternary and member of group 1 with 5 bytes. for {ethernet.dstAddr[23:16]}.
Allocating: Byte 138 is of type ternary and member of group 1 with 5 bytes. for {ethernet.srcAddr[47:40]}.
Allocating: Byte 139 is of type ternary and member of group 2 with 5 bytes. for {ethernet.etherType[15:8]}.
Allocating: Byte 140 is of type ternary and member of group 2 with 5 bytes. for {ig_intr_md.ingress_port[7:0]}.
Allocating: Byte 141 is of type ternary and member of group 2 with 5 bytes. for {ethernet.dstAddr[7:0]}.
Allocating: Byte 142 is of type ternary and member of group 2 with 5 bytes. for {ethernet.srcAddr[39:32]}.
Allocating: Byte 143 is of type ternary and member of group 2 with 5 bytes. for {ethernet.dstAddr[47:40]}.
Formed Ternary Match Key:
{--unused--[3:0], ethernet.dstAddr[47:40], ethernet.srcAddr[39:32], ethernet.dstAddr[7:0], ig_intr_md.ingress_port[7:0], ethernet.etherType[15:8], --version--[1:0], --unused--[1:0], ethernet.srcAddr[47:40], ethernet.dstAddr[23:16], ethernet.etherType[7:0], ethernet.dstAddr[39:24], --unused--[2:0], ig_intr_md.ingress_port[8:8], ethernet.dstAddr[15:8], ethernet.srcAddr[31:0]}

---------------------------------------------
Call to can_any_match_key_fields_be_shared(stage=0, table=table0)
---------------------------------------------
Decided way to allocate for table table0 in stage 0 WAS non_shared

-----------------------------------------
 Call to allocate_ternary_match_key_2
-----------------------------------------
Total crossbar bytes to allocate = 16
Minimum key bytes required by this match key = 16
Allocating: Byte 133 is of type ternary and member of group 0 with 1 bytes
  version/valid in nibble 1 for table table0. for version/valid
{unused[6:0], ig_intr_md.ingress_port[8:8]}.
Allocating: Byte 128 is of type ternary and member of group 0 with 5 bytes. for {ethernet.srcAddr[7:0]}.
Allocating: Byte 129 is of type ternary and member of group 0 with 5 bytes. for {ethernet.srcAddr[15:8]}.
Allocating: Byte 130 is of type ternary and member of group 0 with 5 bytes. for {ethernet.srcAddr[23:16]}.
Allocating: Byte 131 is of type ternary and member of group 0 with 5 bytes. for {ethernet.srcAddr[31:24]}.
Allocating: Byte 132 is of type ternary and member of group 0 with 5 bytes. for {ethernet.dstAddr[15:8]}.
Allocating: Byte 134 is of type ternary and member of group 1 with 5 bytes. for {ethernet.dstAddr[31:24]}.
Allocating: Byte 135 is of type ternary and member of group 1 with 5 bytes. for {ethernet.dstAddr[39:32]}.
Allocating: Byte 136 is of type ternary and member of group 1 with 5 bytes. for {ethernet.etherType[7:0]}.
Allocating: Byte 137 is of type ternary and member of group 1 with 5 bytes. for {ethernet.dstAddr[23:16]}.
Allocating: Byte 138 is of type ternary and member of group 1 with 5 bytes. for {ethernet.srcAddr[47:40]}.
Allocating: Byte 139 is of type ternary and member of group 2 with 5 bytes. for {ethernet.etherType[15:8]}.
Allocating: Byte 140 is of type ternary and member of group 2 with 5 bytes. for {ig_intr_md.ingress_port[7:0]}.
Allocating: Byte 141 is of type ternary and member of group 2 with 5 bytes. for {ethernet.dstAddr[7:0]}.
Allocating: Byte 142 is of type ternary and member of group 2 with 5 bytes. for {ethernet.srcAddr[39:32]}.
Allocating: Byte 143 is of type ternary and member of group 2 with 5 bytes. for {ethernet.dstAddr[47:40]}.
Formed Ternary Match Key:
{--unused--[3:0], ethernet.dstAddr[47:40], ethernet.srcAddr[39:32], ethernet.dstAddr[7:0], ig_intr_md.ingress_port[7:0], ethernet.etherType[15:8], --version--[1:0], --unused--[1:0], ethernet.srcAddr[47:40], ethernet.dstAddr[23:16], ethernet.etherType[7:0], ethernet.dstAddr[39:24], --unused--[2:0], ig_intr_md.ingress_port[8:8], ethernet.dstAddr[15:8], ethernet.srcAddr[31:0]}
Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
For action set_egress_port, formed micro_instruction:
Micro Instruction deposit-field for PHV Container 130 has bit width 23
  Field Src2 [3:0]           : 0x2   (4 bits in instruction bits [3:0])
  Field Src1 [4:0]           : 0x0   (5 bits in instruction bits [8:4])
  Field Src1i [0:0]          : 0x1   (1 bits in instruction bits [9:9])
  Field opcode [0:0]         : 0x1   (1 bits in instruction bits [10:10])
  Field high_bit [3:0]       : 0x8   (4 bits in instruction bits [14:11])
  Field low_bit_lo [0:0]     : 0x0   (1 bits in instruction bits [15:15])
  Field right_rotate [3:0]   : 0x0   (4 bits in instruction bits [19:16])
  Field low_bit_hi [2:0]     : 0x0   (3 bits in instruction bits [22:20])

Allocating Action ALU 2 (16 bits) in stage 0 for match table table0's action set_egress_port
Allocating VLIW Instruction : 0 in stage 0 for match table table0's action set_egress_port
For action send_to_cpu, formed micro_instruction:
Micro Instruction deposit-field for PHV Container 130 has bit width 23
  Field Src2 [3:0]           : 0x2   (4 bits in instruction bits [3:0])
  Field Src1 [4:0]           : 0x0   (5 bits in instruction bits [8:4])
  Field Src1i [0:0]          : 0x1   (1 bits in instruction bits [9:9])
  Field opcode [0:0]         : 0x1   (1 bits in instruction bits [10:10])
  Field high_bit [3:0]       : 0x8   (4 bits in instruction bits [14:11])
  Field low_bit_lo [0:0]     : 0x0   (1 bits in instruction bits [15:15])
  Field right_rotate [3:0]   : 0x0   (4 bits in instruction bits [19:16])
  Field low_bit_hi [2:0]     : 0x0   (3 bits in instruction bits [22:20])

For action send_to_cpu, formed micro_instruction:
Micro Instruction deposit-field for PHV Container 66 has bit width 20
  Field Src2 [3:0]           : 0x2   (4 bits in instruction bits [3:0])
  Field Src1 [4:0]           : 0x19   (5 bits in instruction bits [8:4])
  Field Src1i [0:0]          : 0x0   (1 bits in instruction bits [9:9])
  Field opcode [0:0]         : 0x1   (1 bits in instruction bits [10:10])
  Field high_bit [2:0]       : 0x0   (3 bits in instruction bits [13:11])
  Field low_bit_lo [1:0]     : 0x0   (2 bits in instruction bits [15:14])
  Field right_rotate [2:0]   : 0x0   (3 bits in instruction bits [18:16])
  Field low_bit_hi [0:0]     : 0x0   (1 bits in instruction bits [19:19])

For action send_to_cpu, formed micro_instruction:
Micro Instruction deposit-field for PHV Container 129 has bit width 23
  Field Src2 [3:0]           : 0x1   (4 bits in instruction bits [3:0])
  Field Src1 [4:0]           : 0x0   (5 bits in instruction bits [8:4])
  Field Src1i [0:0]          : 0x0   (1 bits in instruction bits [9:9])
  Field opcode [0:0]         : 0x1   (1 bits in instruction bits [10:10])
  Field high_bit [3:0]       : 0xf   (4 bits in instruction bits [14:11])
  Field low_bit_lo [0:0]     : 0x1   (1 bits in instruction bits [15:15])
  Field right_rotate [3:0]   : 0x9   (4 bits in instruction bits [19:16])
  Field low_bit_hi [2:0]     : 0x3   (3 bits in instruction bits [22:20])

Allocating Action ALU 2 (16 bits) in stage 0 for match table table0's action send_to_cpu
Allocating Action ALU 2 (8 bits) in stage 0 for match table table0's action send_to_cpu
Allocating Action ALU 1 (16 bits) in stage 0 for match table table0's action send_to_cpu
Allocating VLIW Instruction : 1 in stage 0 for match table table0's action send_to_cpu
For action _drop, formed micro_instruction:
Micro Instruction deposit-field for PHV Container 67 has bit width 20
  Field Src2 [3:0]           : 0x3   (4 bits in instruction bits [3:0])
  Field Src1 [4:0]           : 0x19   (5 bits in instruction bits [8:4])
  Field Src1i [0:0]          : 0x0   (1 bits in instruction bits [9:9])
  Field opcode [0:0]         : 0x1   (1 bits in instruction bits [10:10])
  Field high_bit [2:0]       : 0x7   (3 bits in instruction bits [13:11])
  Field low_bit_lo [1:0]     : 0x1   (2 bits in instruction bits [15:14])
  Field right_rotate [2:0]   : 0x3   (3 bits in instruction bits [18:16])
  Field low_bit_hi [0:0]     : 0x1   (1 bits in instruction bits [19:19])

Allocating Action ALU 3 (8 bits) in stage 0 for match table table0's action _drop
Allocating VLIW Instruction : 1 in stage 0 for match table table0's action _drop
Ternary table Pack Format = 
Pack Format:
  table_word_width: 141
  memory_word_width: 47
  entries_per_table_word: 1
  number_memory_units_per_table_word: 3
  entry_list: [
  entry_number : 0
  field_list : [
    ]
       Field --tcam_parity_2-- [1:0]         : in bits [140:139]
       Field --unused-- [3:0]                : in bits [138:135]
       Field ethernet.dstAddr [47:40]        : in bits [134:127]
       Field ethernet.srcAddr [39:32]        : in bits [126:119]
       Field ethernet.dstAddr [7:0]          : in bits [118:111]
       Field ig_intr_md.ingress_port [7:0]   : in bits [110:103]
       Field ethernet.etherType [15:8]       : in bits [102:95]
       Field --tcam_payload_2-- [0:0]        : in bits [94:94]
       Field --tcam_parity_1-- [1:0]         : in bits [93:92]
       Field --version-- [1:0]               : in bits [91:90]
       Field --unused-- [1:0]                : in bits [89:88]
       Field ethernet.srcAddr [47:40]        : in bits [87:80]
       Field ethernet.dstAddr [23:16]        : in bits [79:72]
       Field ethernet.etherType [7:0]        : in bits [71:64]
       Field ethernet.dstAddr [39:24]        : in bits [63:48]
       Field --tcam_payload_1-- [0:0]        : in bits [47:47]
       Field --tcam_parity_0-- [1:0]         : in bits [46:45]
       Field --unused-- [2:0]                : in bits [44:42]
       Field ig_intr_md.ingress_port [8:8]   : in bits [41:41]
       Field ethernet.dstAddr [15:8]         : in bits [40:33]
       Field ethernet.srcAddr [31:0]         : in bits [32:1]
       Field --tcam_payload_0-- [0:0]        : in bits [0:0]
]


----------------------------------------------
Call to Allocate P4 Table with table process_packet_out_table__action__, number_entries = 1024, table id = None, and match type = exact
  Allocating in stage 0
----------------------------------------------

ram_size_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0

immediate_size_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0

hash_to_phv_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0

total action ram packing size = [0, 0, 0]
action_ram_packing:
  action _process_packet_out has []
total action ram packing size = [0, 0, 0]
action_ram_packing:
  action _process_packet_out has []
total action ram packing size = [0, 0, 0]
action_ram_packing:
  action _process_packet_out has []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
Allocating Action Logical Table ID 1 in stage 0

----------------------------------------------
Call to Allocate P4 Table with table process_packet_out_table, number_entries = 1024, table id = None, and match type = exact
  Allocating in stage 0
----------------------------------------------

Logical Table ID in stage 0 was not supplied by table placement for table process_packet_out_table.
Allocating Logical Table ID 1 in stage 0
Allocating Table Type ID 0 of type exact in stage 0
Match Overhead:
  Field --version_valid-- [3:0] (4 bits)

Logical Table ID in stage 0 was not supplied by table placement for table process_packet_out_table.
Allocating Logical Table ID 1 in stage 0
Allocating Table Type ID 0 of type exact in stage 0
Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
Match Table Resource Request is:
SRAM Resource Request for table process_packet_out_table (of type match), with 0 ways wants 0 rams.
Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
For action _process_packet_out, formed micro_instruction:
Micro Instruction deposit-field for PHV Container 130 has bit width 23
  Field Src2 [3:0]           : 0x2   (4 bits in instruction bits [3:0])
  Field Src1 [4:0]           : 0x1   (5 bits in instruction bits [8:4])
  Field Src1i [0:0]          : 0x0   (1 bits in instruction bits [9:9])
  Field opcode [0:0]         : 0x1   (1 bits in instruction bits [10:10])
  Field high_bit [3:0]       : 0x8   (4 bits in instruction bits [14:11])
  Field low_bit_lo [0:0]     : 0x0   (1 bits in instruction bits [15:15])
  Field right_rotate [3:0]   : 0x7   (4 bits in instruction bits [19:16])
  Field low_bit_hi [2:0]     : 0x0   (3 bits in instruction bits [22:20])

For action _process_packet_out, formed micro_instruction:
Micro Instruction deposit-field for PHV Container 66 has bit width 20
  Field Src2 [3:0]           : 0x2   (4 bits in instruction bits [3:0])
  Field Src1 [4:0]           : 0x18   (5 bits in instruction bits [8:4])
  Field Src1i [0:0]          : 0x0   (1 bits in instruction bits [9:9])
  Field opcode [0:0]         : 0x1   (1 bits in instruction bits [10:10])
  Field high_bit [2:0]       : 0x1   (3 bits in instruction bits [13:11])
  Field low_bit_lo [1:0]     : 0x1   (2 bits in instruction bits [15:14])
  Field right_rotate [2:0]   : 0x7   (3 bits in instruction bits [18:16])
  Field low_bit_hi [0:0]     : 0x0   (1 bits in instruction bits [19:19])

Allocating Action ALU 2 (16 bits) in stage 0 for match table process_packet_out_table's action _process_packet_out
Allocating Action ALU 2 (8 bits) in stage 0 for match table process_packet_out_table's action _process_packet_out
Allocating VLIW Instruction : 2 in stage 0 for match table process_packet_out_table's action _process_packet_out

----------------------------------------------
Call to Allocate P4 Table with table ingress_port_count_table__action__, number_entries = 1024, table id = None, and match type = exact
  Allocating in stage 1
----------------------------------------------

ram_size_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0

immediate_size_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0

hash_to_phv_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0

total action ram packing size = [0, 0, 0]
action_ram_packing:
  action count_ingress has []
total action ram packing size = [0, 0, 0]
action_ram_packing:
  action count_ingress has []
total action ram packing size = [0, 0, 0]
action_ram_packing:
  action count_ingress has []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
Allocating Action Logical Table ID 0 in stage 1

----------------------------------------------
Call to Allocate P4 Table with table ingress_port_counter, number_entries = 510, table id = None, and match type = exact
  Allocating in stage 1
----------------------------------------------

stat_stage_table referenced: indirect
stat Table Resource Request is:
SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams.
Sram Resource Request for P4 table ingress_port_counter with handle 67108865 of type statistics in stage 1
  table_type : statistics
  rams_for_width : 1
  use_stash : False
  number_ways : 1
  way #0
  SRAM Request Group 0
      rams_for_depth : 2
      map_rams : 0
      way_number : 0
      ram_word_select_bits : 0
      ram_enable_select_bits : 0


----------------------------------------------
Call to Allocate P4 Table with table ingress_port_count_table, number_entries = 1024, table id = None, and match type = exact
  Allocating in stage 1
----------------------------------------------

Logical Table ID in stage 1 was not supplied by table placement for table ingress_port_count_table.
Allocating Logical Table ID 0 in stage 1
Allocating Table Type ID 0 of type exact in stage 1
Match Overhead:
  Field --version_valid-- [3:0] (4 bits)
  Field --instruction_address-- [1:0] (2 bits)
  Field --statistics_pointer-- [19:0] (20 bits)

Logical Table ID in stage 1 was not supplied by table placement for table ingress_port_count_table.
Allocating Logical Table ID 0 in stage 1
Allocating Table Type ID 0 of type exact in stage 1
Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
Match Table Resource Request is:
SRAM Resource Request for table ingress_port_count_table (of type match), with 0 ways wants 0 rams.
Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
No micro instructions needed for action count_ingress executed from table ingress_port_count_table.
Allocating Action ALU 0 (32 bits) in stage 1 for match table ingress_port_count_table's action count_ingress
Allocating VLIW Instruction : 0 in stage 1 for match table ingress_port_count_table's action count_ingress

----------------------------------------------
Call to Allocate P4 Table with table egress_port_count_table__action__, number_entries = 1024, table id = None, and match type = exact
  Allocating in stage 1
----------------------------------------------

ram_size_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0

immediate_size_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0

hash_to_phv_matrix = 
 (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
       0              0              0               0                0               0                0                0        # 0

total action ram packing size = [0, 0, 0]
action_ram_packing:
  action count_egress has []
total action ram packing size = [0, 0, 0]
action_ram_packing:
  action count_egress has []
total action ram packing size = [0, 0, 0]
action_ram_packing:
  action count_egress has []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
byte_enables = []
After allocation of 32s, available_slots is []
final packing is []
Allocating Action Logical Table ID 1 in stage 1

----------------------------------------------
Call to Allocate P4 Table with table egress_port_counter, number_entries = 510, table id = None, and match type = exact
  Allocating in stage 1
----------------------------------------------

stat_stage_table referenced: indirect
stat Table Resource Request is:
SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams.
Sram Resource Request for P4 table egress_port_counter with handle 67108866 of type statistics in stage 1
  table_type : statistics
  rams_for_width : 1
  use_stash : False
  number_ways : 1
  way #0
  SRAM Request Group 0
      rams_for_depth : 2
      map_rams : 0
      way_number : 0
      ram_word_select_bits : 0
      ram_enable_select_bits : 0

Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.

----------------------------------------------
Call to Allocate P4 Table with table egress_port_count_table, number_entries = 1024, table id = None, and match type = exact
  Allocating in stage 1
----------------------------------------------

Logical Table ID in stage 1 was not supplied by table placement for table egress_port_count_table.
Allocating Logical Table ID 1 in stage 1
Allocating Table Type ID 1 of type exact in stage 1
Match Overhead:
  Field --version_valid-- [3:0] (4 bits)
  Field --statistics_pointer-- [19:0] (20 bits)

Logical Table ID in stage 1 was not supplied by table placement for table egress_port_count_table.
Allocating Logical Table ID 1 in stage 1
Allocating Table Type ID 1 of type exact in stage 1
Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
Match Table Resource Request is:
SRAM Resource Request for table egress_port_count_table (of type match), with 0 ways wants 0 rams.
Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
No micro instructions needed for action count_egress executed from table egress_port_count_table.
Allocating Action ALU 0 (32 bits) in stage 1 for match table egress_port_count_table's action count_egress
Allocating VLIW Instruction : 0 in stage 1 for match table egress_port_count_table's action count_egress
Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
Cannot find table object for 'process_packet_out_table_always_true_condition'.
Field ig_intr_md_for_tm.ucast_egress_port not contiguous on gateway input
Field ig_intr_md_for_tm.ucast_egress_port not contiguous on gateway input
Writing configuration registers: regs.match_action_stage.00
Writing configuration registers: regs.match_action_stage.01
Writing configuration registers: regs.match_action_stage.02
Writing configuration registers: regs.match_action_stage.03
Writing configuration registers: regs.match_action_stage.04
Writing configuration registers: regs.match_action_stage.05
Writing configuration registers: regs.match_action_stage.06
Writing configuration registers: regs.match_action_stage.07
Writing configuration registers: regs.match_action_stage.08
Writing configuration registers: regs.match_action_stage.09
Writing configuration registers: regs.match_action_stage.0a
Writing configuration registers: regs.match_action_stage.0b