diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/montara/logs/mau.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/montara/logs/mau.log
index 8b5f74c..4628e6b 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/montara/logs/mau.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/montara/logs/mau.log
@@ -1,27 +1,27 @@
 +---------------------------------------------------------------------+
 |  Log file: mau.log                                                  |
 |  Compiler version: 5.1.0 (fca32d1)                                  |
-|  Created on: Thu Sep  7 14:49:38 2017                               |
+|  Created on: Fri Sep  8 08:26:04 2017                               |
 +---------------------------------------------------------------------+
 
 Match Table table0 did not specify the number of entries required. A default value (512) will be used.
 Match Table ecmp_group_table did not specify the number of entries required. A default value (1024) will be used.
 Match Entry Table table0 has already been associated with stat Table table0_counter.
 Match Entry Table ecmp_group_table has already been associated with stat Table ecmp_group_table_counter.
-Cannot implement ingress_pkt in phase 0 resources because table does not have the correct condition
+Cannot implement table0 in phase 0 resources because table uses side effect tables.
 Match Table table0 did not specify the number of entries required. A default value (512) will be used.
 Match Table ecmp_group_table did not specify the number of entries required. A default value (1024) will be used.
 Match Entry Table table0 has already been associated with stat Table table0_counter.
 Match Entry Table ecmp_group_table has already been associated with stat Table ecmp_group_table_counter.
-Cannot implement ingress_pkt in phase 0 resources because table does not have the correct condition
+Cannot implement table0 in phase 0 resources because table uses side effect tables.
 Match Table table0 did not specify the number of entries required. A default value (512) will be used.
 Match Table ecmp_group_table did not specify the number of entries required. A default value (1024) will be used.
-POV/metadata bridge containers added between ingress/egress: [0, 64, 128]
+POV/metadata bridge containers added between ingress/egress: [0]
 Metadata bridge_ingress_intrinsic containers added between ingress/egress: [128]
 Match Entry Table table0 has already been associated with stat Table table0_counter.
 Match Entry Table ecmp_group_table has already been associated with stat Table ecmp_group_table_counter.
 Match table ingress_port_count_table has no match key fields
-Cannot use hash-action for table ingress_port_count_table with no key because the number of entries required by side-effect table ingress_port_counter is not a power of 2 -- 254.
+Cannot use hash-action for table ingress_port_count_table with no key because the number of entries required by side-effect table ingress_port_counter is not a power of 2 -- 510.
 
 ##########################################
   Call to decide_action_data_placement(stage=0, table=ingress_port_count_table)
@@ -83,7 +83,7 @@
 Best Ram Usage is 97 rams
 Best Immediate placement is 0 bits
 Match table egress_port_count_table has no match key fields
-Cannot use hash-action for table egress_port_count_table with no key because the number of entries required by side-effect table egress_port_counter is not a power of 2 -- 254.
+Cannot use hash-action for table egress_port_count_table with no key because the number of entries required by side-effect table egress_port_counter is not a power of 2 -- 510.
 
 ##########################################
   Call to decide_action_data_placement(stage=0, table=egress_port_count_table)
@@ -146,16 +146,16 @@
 Best Immediate placement is 0 bits
 
 ##########################################
-  Call to decide_action_data_placement(stage=0, table=ingress_pkt)
+  Call to decide_action_data_placement(stage=0, table=process_packet_out_table)
 ##########################################
 
 
 Max immediate bits used in any action is 0 bits.
-Overhead bit width for table ingress_pkt is 2 bits.
+Overhead bit width for table process_packet_out_table is 0 bits.
 Bits available in overhead for non-essential immediate data is 32 bits.
 ~~~~~~~~~~~~~~~~~~~~~
  Examining placing 0 bits in match overhead
-Overhead bit width for table ingress_pkt is 2 bits.
+Overhead bit width for table process_packet_out_table is 0 bits.
 Overhead SRAMs to use = 97
   Entries requested = 1024  and match entries get = 0
 ram_size_matrix = 
@@ -172,73 +172,13 @@
 
 total action ram packing size = [0, 0, 0]
 action_ram_packing:
-  action _packet_out has []
+  action _process_packet_out has []
 total action ram packing size = [0, 0, 0]
 action_ram_packing:
-  action _packet_out has []
+  action _process_packet_out has []
 total action ram packing size = [0, 0, 0]
 action_ram_packing:
-  action _packet_out has []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-Action Data SRAMs to use = 0
-TODO: Total RAMs use when put 0 bits in match overhead: 97
-TODO: Total RAMs use when put 0 bits in match overhead: 97
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 8 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 16 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 24 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 32 bits in match overhead
-
-##########################################
-
-Best Ram Usage is 97 rams
-Best Immediate placement is 0 bits
-
-##########################################
-  Call to decide_action_data_placement(stage=0, table=egress_pkt)
-##########################################
-
-
-Max immediate bits used in any action is 0 bits.
-Overhead bit width for table egress_pkt is 2 bits.
-Bits available in overhead for non-essential immediate data is 32 bits.
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 0 bits in match overhead
-Overhead bit width for table egress_pkt is 2 bits.
-Overhead SRAMs to use = 97
-  Entries requested = 1024  and match entries get = 0
-ram_size_matrix = 
- (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
-       0              0              0               0                0               0                0                0        # 0
-
-immediate_size_matrix = 
- (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
-       0              0              0               0                0               0                0                0        # 0
-
-hash_to_phv_matrix = 
- (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
-       0              0              0               0                0               0                0                0        # 0
-
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
-  action add_packet_in_hdr has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
-  action add_packet_in_hdr has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
-  action add_packet_in_hdr has []
+  action _process_packet_out has []
 byte_enables = []
 After allocation of 32s, available_slots is []
 final packing is []
@@ -501,100 +441,18 @@
 
 Best Ram Usage is 3 rams
 Best Immediate placement is 16 bits
-Cannot implement ingress_pkt in phase 0 resources because table does not have the correct condition
-
-----------------------------------------------
-Call to Allocate P4 Table with table ingress_pkt__action__, number_entries = 1024, table id = None, and match type = exact
-  Allocating in stage 0
-----------------------------------------------
-
-ram_size_matrix = 
- (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
-       0              0              0               0                0               0                0                0        # 0
-
-immediate_size_matrix = 
- (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
-       0              0              0               0                0               0                0                0        # 0
-
-hash_to_phv_matrix = 
- (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
-       0              0              0               0                0               0                0                0        # 0
-
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
-  action _packet_out has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
-  action _packet_out has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
-  action _packet_out has []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-Allocating Action Logical Table ID 0 in stage 0
-
-----------------------------------------------
-Call to Allocate P4 Table with table ingress_pkt, number_entries = 1024, table id = None, and match type = exact
-  Allocating in stage 0
-----------------------------------------------
-
-Logical Table ID in stage 0 was not supplied by table placement for table ingress_pkt.
-Allocating Logical Table ID 0 in stage 0
-Allocating Table Type ID 0 of type exact in stage 0
-Match Overhead:
-  Field --version_valid-- [3:0] (4 bits)
-  Field --instruction_address-- [1:0] (2 bits)
-
-Logical Table ID in stage 0 was not supplied by table placement for table ingress_pkt.
-Allocating Logical Table ID 0 in stage 0
-Allocating Table Type ID 0 of type exact in stage 0
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
-Match Table Resource Request is:
-SRAM Resource Request for table ingress_pkt (of type match), with 0 ways wants 0 rams.
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
-For action _packet_out, formed micro_instruction:
-Micro Instruction deposit-field for PHV Container 130 has bit width 23
-  Field Src2 [3:0]           : 0x2   (4 bits in instruction bits [3:0])
-  Field Src1 [4:0]           : 0x1   (5 bits in instruction bits [8:4])
-  Field Src1i [0:0]          : 0x0   (1 bits in instruction bits [9:9])
-  Field opcode [0:0]         : 0x1   (1 bits in instruction bits [10:10])
-  Field high_bit [3:0]       : 0x8   (4 bits in instruction bits [14:11])
-  Field low_bit_lo [0:0]     : 0x0   (1 bits in instruction bits [15:15])
-  Field right_rotate [3:0]   : 0x7   (4 bits in instruction bits [19:16])
-  Field low_bit_hi [2:0]     : 0x0   (3 bits in instruction bits [22:20])
-
-For action _packet_out, formed micro_instruction:
-Micro Instruction deposit-field for PHV Container 68 has bit width 20
-  Field Src2 [3:0]           : 0x4   (4 bits in instruction bits [3:0])
-  Field Src1 [4:0]           : 0x18   (5 bits in instruction bits [8:4])
-  Field Src1i [0:0]          : 0x0   (1 bits in instruction bits [9:9])
-  Field opcode [0:0]         : 0x1   (1 bits in instruction bits [10:10])
-  Field high_bit [2:0]       : 0x1   (3 bits in instruction bits [13:11])
-  Field low_bit_lo [1:0]     : 0x1   (2 bits in instruction bits [15:14])
-  Field right_rotate [2:0]   : 0x7   (3 bits in instruction bits [18:16])
-  Field low_bit_hi [0:0]     : 0x0   (1 bits in instruction bits [19:19])
-
-Allocating Action ALU 2 (16 bits) in stage 0 for match table ingress_pkt's action _packet_out
-Allocating Action ALU 4 (8 bits) in stage 0 for match table ingress_pkt's action _packet_out
-Allocating VLIW Instruction : 0 in stage 0 for match table ingress_pkt's action _packet_out
+Cannot implement table0 in phase 0 resources because table uses side effect tables.
 
 ----------------------------------------------
 Call to Allocate P4 Table with table table0__action__, number_entries = 512, table id = None, and match type = exact
-  Allocating in stage 1
+  Allocating in stage 0
 ----------------------------------------------
 
 ram_size_matrix = 
  (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
        0              0              0               1                0               0                0                0        # 0
        0              0              0               1                0               0                0                0        # 1
-       0              0              0               0                0               0                0                0        # 2
+       0              0              0               1                0               0                0                0        # 2
        0              0              0               0                0               0                0                0        # 3
 
 immediate_size_matrix = 
@@ -615,7 +473,7 @@
 action_ram_packing:
   action set_egress_port has [(16, 16, False)]
   action ecmp_group has [(16, 16, False)]
-  action send_to_cpu has []
+  action send_to_cpu has [(16, 16, False)]
   action _drop has []
 total action ram packing size = [16, 0, 0]
 action_ram_packing:
@@ -630,14 +488,14 @@
   action send_to_cpu has [(16, 0, False)]
   action _drop has [(16, 0, False)]
 byte_enables = [1, 1]
-Allocating Action Parameter Bus Byte 32 in stage 1 for Byte 0 of 16-bit constant
-Allocating Action Parameter Bus Byte 33 in stage 1 for Byte 1 of 16-bit constant
-Allocating Action Parameter Bus Byte 34 in stage 1 for Byte 0 of 16-bit constant
-Allocating Action Parameter Bus Byte 35 in stage 1 for Byte 1 of 16-bit constant
+Allocating Action Parameter Bus Byte 32 in stage 0 for Byte 0 of 16-bit constant
+Allocating Action Parameter Bus Byte 33 in stage 0 for Byte 1 of 16-bit constant
+Allocating Action Parameter Bus Byte 34 in stage 0 for Byte 0 of 16-bit constant
+Allocating Action Parameter Bus Byte 35 in stage 0 for Byte 1 of 16-bit constant
 After allocation of 32s, available_slots is [(16, 0, 0), (32, 8, 0), (16, 1, 16)]
 final packing is [(16, 16, False)]
 final packing is [(16, 16, False)]
-final packing is []
+final packing is [(16, 16, False)]
 final packing is []
 byte_enables = []
 After allocation of 32s, available_slots is []
@@ -646,10 +504,10 @@
 final packing is []
 final packing is []
 byte_enables = [1, 1]
-Allocating Action Parameter Bus Byte 36 in stage 1 for Byte 0 of 16-bit constant
-Allocating Action Parameter Bus Byte 37 in stage 1 for Byte 1 of 16-bit constant
-Allocating Action Parameter Bus Byte 38 in stage 1 for Byte 0 of 16-bit constant
-Allocating Action Parameter Bus Byte 39 in stage 1 for Byte 1 of 16-bit constant
+Allocating Action Parameter Bus Byte 36 in stage 0 for Byte 0 of 16-bit constant
+Allocating Action Parameter Bus Byte 37 in stage 0 for Byte 1 of 16-bit constant
+Allocating Action Parameter Bus Byte 38 in stage 0 for Byte 0 of 16-bit constant
+Allocating Action Parameter Bus Byte 39 in stage 0 for Byte 1 of 16-bit constant
 After allocation of 32s, available_slots is [(16, 2, 0), (32, 9, 0), (16, 3, 16)]
 final packing is [(16, 0, False)]
 final packing is [(16, 16, False)]
@@ -688,8 +546,8 @@
     hash_bits_in_units = OrderedDict([(0, [0])])
     address_left_shift = 0
 -------------------
-Allocating Hash Distribution Group 0/0 for table table0__action__ in stage 1.
-Allocating Hash Bit 0 in hash match group 0 for table table0__action__ in stage 1.
+Allocating Hash Distribution Group 0/0 for table table0__action__ in stage 0.
+Allocating Hash Bit 0 in hash match group 0 for table table0__action__ in stage 0.
 seed = 0x7bd5c66f
 set the seed to be [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
 Hash Function 0
@@ -746,17 +604,17 @@
 hash_bit_50 = 0
 hash_bit_51 = 0
 
-Allocating Action Logical Table ID 0 in stage 1
+Allocating Action Logical Table ID 0 in stage 0
 
 ----------------------------------------------
 Call to Allocate P4 Table with table table0_counter, number_entries = 512, table id = None, and match type = exact
-  Allocating in stage 1
+  Allocating in stage 0
 ----------------------------------------------
 
 stat_stage_table referenced: direct
 stat Table Resource Request is:
 SRAM Resource Request for table table0_counter (of type statistics), with 1 ways wants 2 rams.
-Sram Resource Request for P4 table table0_counter with handle 67108867 of type statistics in stage 1
+Sram Resource Request for P4 table table0_counter with handle 67108867 of type statistics in stage 0
   table_type : statistics
   rams_for_width : 1
   use_stash : False
@@ -772,12 +630,12 @@
 
 ----------------------------------------------
 Call to Allocate P4 Table with table table0, number_entries = 512, table id = None, and match type = ternary
-  Allocating in stage 1
+  Allocating in stage 0
 ----------------------------------------------
 
-Logical Table ID in stage 1 was not supplied by table placement for table table0.
-Allocating Logical Table ID 0 in stage 1
-Allocating Table Type ID 0 of type ternary in stage 1
+Logical Table ID in stage 0 was not supplied by table placement for table table0.
+Allocating Logical Table ID 0 in stage 0
+Allocating Table Type ID 0 of type ternary in stage 0
 
 -----------------------------------------
  Call to allocate_ternary_match_key_2
@@ -806,9 +664,9 @@
 {--unused--[3:0], ethernet.dstAddr[47:40], ethernet.srcAddr[39:32], ethernet.dstAddr[7:0], ig_intr_md.ingress_port[7:0], ethernet.etherType[15:8], --version--[1:0], --unused--[1:0], ethernet.srcAddr[47:40], ethernet.dstAddr[23:16], ethernet.etherType[7:0], ethernet.dstAddr[39:24], --unused--[2:0], ig_intr_md.ingress_port[8:8], ethernet.dstAddr[15:8], ethernet.srcAddr[31:0]}
 
 ---------------------------------------------
-Call to can_any_match_key_fields_be_shared(stage=1, table=table0)
+Call to can_any_match_key_fields_be_shared(stage=0, table=table0)
 ---------------------------------------------
-Decided way to allocate for table table0 in stage 1 WAS non_shared
+Decided way to allocate for table table0 in stage 0 WAS non_shared
 
 -----------------------------------------
  Call to allocate_ternary_match_key_2
@@ -849,8 +707,8 @@
   Field right_rotate [3:0]   : 0x0   (4 bits in instruction bits [19:16])
   Field low_bit_hi [2:0]     : 0x0   (3 bits in instruction bits [22:20])
 
-Allocating Action ALU 2 (16 bits) in stage 1 for match table table0's action set_egress_port
-Allocating VLIW Instruction : 0 in stage 1 for match table table0's action set_egress_port
+Allocating Action ALU 2 (16 bits) in stage 0 for match table table0's action set_egress_port
+Allocating VLIW Instruction : 0 in stage 0 for match table table0's action set_egress_port
 For action ecmp_group, formed micro_instruction:
 Micro Instruction alu_a for PHV Container 134 has bit width 23
   Field Src2 [3:0]     : 0x6   (4 bits in instruction bits [3:0])
@@ -867,12 +725,23 @@
   Field opcode [9:0]   : 0x31e   (10 bits in instruction bits [19:10])
   Field unused [2:0]   : 0x0   (3 bits in instruction bits [22:20])
 
-Allocating Action ALU 6 (16 bits) in stage 1 for match table table0's action ecmp_group
-Allocating Action ALU 7 (16 bits) in stage 1 for match table table0's action ecmp_group
-Allocating VLIW Instruction : 1 in stage 1 for match table table0's action ecmp_group
+Allocating Action ALU 6 (16 bits) in stage 0 for match table table0's action ecmp_group
+Allocating Action ALU 7 (16 bits) in stage 0 for match table table0's action ecmp_group
+Allocating VLIW Instruction : 1 in stage 0 for match table table0's action ecmp_group
 For action send_to_cpu, formed micro_instruction:
-Micro Instruction deposit-field for PHV Container 64 has bit width 20
-  Field Src2 [3:0]           : 0x0   (4 bits in instruction bits [3:0])
+Micro Instruction deposit-field for PHV Container 130 has bit width 23
+  Field Src2 [3:0]           : 0x2   (4 bits in instruction bits [3:0])
+  Field Src1 [4:0]           : 0x0   (5 bits in instruction bits [8:4])
+  Field Src1i [0:0]          : 0x1   (1 bits in instruction bits [9:9])
+  Field opcode [0:0]         : 0x1   (1 bits in instruction bits [10:10])
+  Field high_bit [3:0]       : 0x8   (4 bits in instruction bits [14:11])
+  Field low_bit_lo [0:0]     : 0x0   (1 bits in instruction bits [15:15])
+  Field right_rotate [3:0]   : 0x0   (4 bits in instruction bits [19:16])
+  Field low_bit_hi [2:0]     : 0x0   (3 bits in instruction bits [22:20])
+
+For action send_to_cpu, formed micro_instruction:
+Micro Instruction deposit-field for PHV Container 67 has bit width 20
+  Field Src2 [3:0]           : 0x3   (4 bits in instruction bits [3:0])
   Field Src1 [4:0]           : 0x19   (5 bits in instruction bits [8:4])
   Field Src1i [0:0]          : 0x0   (1 bits in instruction bits [9:9])
   Field opcode [0:0]         : 0x1   (1 bits in instruction bits [10:10])
@@ -881,11 +750,24 @@
   Field right_rotate [2:0]   : 0x0   (3 bits in instruction bits [18:16])
   Field low_bit_hi [0:0]     : 0x0   (1 bits in instruction bits [19:19])
 
-Allocating Action ALU 0 (8 bits) in stage 1 for match table table0's action send_to_cpu
-Allocating VLIW Instruction : 1 in stage 1 for match table table0's action send_to_cpu
+For action send_to_cpu, formed micro_instruction:
+Micro Instruction deposit-field for PHV Container 129 has bit width 23
+  Field Src2 [3:0]           : 0x1   (4 bits in instruction bits [3:0])
+  Field Src1 [4:0]           : 0x0   (5 bits in instruction bits [8:4])
+  Field Src1i [0:0]          : 0x0   (1 bits in instruction bits [9:9])
+  Field opcode [0:0]         : 0x1   (1 bits in instruction bits [10:10])
+  Field high_bit [3:0]       : 0xf   (4 bits in instruction bits [14:11])
+  Field low_bit_lo [0:0]     : 0x1   (1 bits in instruction bits [15:15])
+  Field right_rotate [3:0]   : 0x9   (4 bits in instruction bits [19:16])
+  Field low_bit_hi [2:0]     : 0x3   (3 bits in instruction bits [22:20])
+
+Allocating Action ALU 2 (16 bits) in stage 0 for match table table0's action send_to_cpu
+Allocating Action ALU 3 (8 bits) in stage 0 for match table table0's action send_to_cpu
+Allocating Action ALU 1 (16 bits) in stage 0 for match table table0's action send_to_cpu
+Allocating VLIW Instruction : 1 in stage 0 for match table table0's action send_to_cpu
 For action _drop, formed micro_instruction:
-Micro Instruction deposit-field for PHV Container 69 has bit width 20
-  Field Src2 [3:0]           : 0x5   (4 bits in instruction bits [3:0])
+Micro Instruction deposit-field for PHV Container 68 has bit width 20
+  Field Src2 [3:0]           : 0x4   (4 bits in instruction bits [3:0])
   Field Src1 [4:0]           : 0x19   (5 bits in instruction bits [8:4])
   Field Src1i [0:0]          : 0x0   (1 bits in instruction bits [9:9])
   Field opcode [0:0]         : 0x1   (1 bits in instruction bits [10:10])
@@ -894,8 +776,8 @@
   Field right_rotate [2:0]   : 0x3   (3 bits in instruction bits [18:16])
   Field low_bit_hi [0:0]     : 0x1   (1 bits in instruction bits [19:19])
 
-Allocating Action ALU 5 (8 bits) in stage 1 for match table table0's action _drop
-Allocating VLIW Instruction : 2 in stage 1 for match table table0's action _drop
+Allocating Action ALU 4 (8 bits) in stage 0 for match table table0's action _drop
+Allocating VLIW Instruction : 2 in stage 0 for match table table0's action _drop
 Ternary table Pack Format = 
 Pack Format:
   table_word_width: 141
@@ -932,8 +814,89 @@
 
 
 ----------------------------------------------
+Call to Allocate P4 Table with table process_packet_out_table__action__, number_entries = 1024, table id = None, and match type = exact
+  Allocating in stage 0
+----------------------------------------------
+
+ram_size_matrix = 
+ (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
+       0              0              0               0                0               0                0                0        # 0
+
+immediate_size_matrix = 
+ (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
+       0              0              0               0                0               0                0                0        # 0
+
+hash_to_phv_matrix = 
+ (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
+       0              0              0               0                0               0                0                0        # 0
+
+total action ram packing size = [0, 0, 0]
+action_ram_packing:
+  action _process_packet_out has []
+total action ram packing size = [0, 0, 0]
+action_ram_packing:
+  action _process_packet_out has []
+total action ram packing size = [0, 0, 0]
+action_ram_packing:
+  action _process_packet_out has []
+byte_enables = []
+After allocation of 32s, available_slots is []
+final packing is []
+byte_enables = []
+After allocation of 32s, available_slots is []
+final packing is []
+byte_enables = []
+After allocation of 32s, available_slots is []
+final packing is []
+Allocating Action Logical Table ID 1 in stage 0
+
+----------------------------------------------
+Call to Allocate P4 Table with table process_packet_out_table, number_entries = 1024, table id = None, and match type = exact
+  Allocating in stage 0
+----------------------------------------------
+
+Logical Table ID in stage 0 was not supplied by table placement for table process_packet_out_table.
+Allocating Logical Table ID 1 in stage 0
+Allocating Table Type ID 0 of type exact in stage 0
+Match Overhead:
+  Field --version_valid-- [3:0] (4 bits)
+
+Logical Table ID in stage 0 was not supplied by table placement for table process_packet_out_table.
+Allocating Logical Table ID 1 in stage 0
+Allocating Table Type ID 0 of type exact in stage 0
+Allocating: Byte 12 is of type exact and member of group 0 (parity group 1) with 16 bytes. for {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
+Match Table Resource Request is:
+SRAM Resource Request for table process_packet_out_table (of type match), with 0 ways wants 0 rams.
+Allocating: Byte 12 is of type exact and member of group 0 (parity group 1) with 16 bytes. for {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
+For action _process_packet_out, formed micro_instruction:
+Micro Instruction deposit-field for PHV Container 130 has bit width 23
+  Field Src2 [3:0]           : 0x2   (4 bits in instruction bits [3:0])
+  Field Src1 [4:0]           : 0x1   (5 bits in instruction bits [8:4])
+  Field Src1i [0:0]          : 0x0   (1 bits in instruction bits [9:9])
+  Field opcode [0:0]         : 0x1   (1 bits in instruction bits [10:10])
+  Field high_bit [3:0]       : 0x8   (4 bits in instruction bits [14:11])
+  Field low_bit_lo [0:0]     : 0x0   (1 bits in instruction bits [15:15])
+  Field right_rotate [3:0]   : 0x7   (4 bits in instruction bits [19:16])
+  Field low_bit_hi [2:0]     : 0x0   (3 bits in instruction bits [22:20])
+
+For action _process_packet_out, formed micro_instruction:
+Micro Instruction deposit-field for PHV Container 67 has bit width 20
+  Field Src2 [3:0]           : 0x3   (4 bits in instruction bits [3:0])
+  Field Src1 [4:0]           : 0x18   (5 bits in instruction bits [8:4])
+  Field Src1i [0:0]          : 0x0   (1 bits in instruction bits [9:9])
+  Field opcode [0:0]         : 0x1   (1 bits in instruction bits [10:10])
+  Field high_bit [2:0]       : 0x1   (3 bits in instruction bits [13:11])
+  Field low_bit_lo [1:0]     : 0x1   (2 bits in instruction bits [15:14])
+  Field right_rotate [2:0]   : 0x7   (3 bits in instruction bits [18:16])
+  Field low_bit_hi [0:0]     : 0x0   (1 bits in instruction bits [19:19])
+
+Allocating Action ALU 2 (16 bits) in stage 0 for match table process_packet_out_table's action _process_packet_out
+Allocating Action ALU 3 (8 bits) in stage 0 for match table process_packet_out_table's action _process_packet_out
+Allocating VLIW Instruction : 2 in stage 0 for match table process_packet_out_table's action _process_packet_out
+
+----------------------------------------------
 Call to Allocate P4 Table with table ecmp_group_table__action__, number_entries = 1024, table id = None, and match type = exact
-  Allocating in stage 2
+  Allocating in stage 1
 ----------------------------------------------
 
 ram_size_matrix = 
@@ -961,26 +924,26 @@
 After allocation of 32s, available_slots is []
 final packing is []
 byte_enables = [1, 1]
-Allocating Action Parameter Bus Byte 32 in stage 2 for Byte 0 of 16-bit constant
-Allocating Action Parameter Bus Byte 33 in stage 2 for Byte 1 of 16-bit constant
-Allocating Action Parameter Bus Byte 34 in stage 2 for Byte 0 of 16-bit constant
-Allocating Action Parameter Bus Byte 35 in stage 2 for Byte 1 of 16-bit constant
+Allocating Action Parameter Bus Byte 32 in stage 1 for Byte 0 of 16-bit constant
+Allocating Action Parameter Bus Byte 33 in stage 1 for Byte 1 of 16-bit constant
+Allocating Action Parameter Bus Byte 34 in stage 1 for Byte 0 of 16-bit constant
+Allocating Action Parameter Bus Byte 35 in stage 1 for Byte 1 of 16-bit constant
 After allocation of 32s, available_slots is [(16, 0, 0), (32, 8, 0), (16, 1, 16)]
 final packing is [(16, 16, False)]
 byte_enables = []
 After allocation of 32s, available_slots is []
 final packing is []
-Allocating Action Logical Table ID 0 in stage 2
+Allocating Action Logical Table ID 0 in stage 1
 
 ----------------------------------------------
 Call to Allocate P4 Table with table ecmp_group_table_counter, number_entries = 1024, table id = None, and match type = exact
-  Allocating in stage 2
+  Allocating in stage 1
 ----------------------------------------------
 
 stat_stage_table referenced: direct
 stat Table Resource Request is:
 SRAM Resource Request for table ecmp_group_table_counter (of type statistics), with 1 ways wants 2 rams.
-Sram Resource Request for P4 table ecmp_group_table_counter with handle 67108868 of type statistics in stage 2
+Sram Resource Request for P4 table ecmp_group_table_counter with handle 67108868 of type statistics in stage 1
   table_type : statistics
   rams_for_width : 1
   use_stash : False
@@ -996,12 +959,12 @@
 
 ----------------------------------------------
 Call to Allocate P4 Table with table ecmp_group_table, number_entries = 1024, table id = None, and match type = exact
-  Allocating in stage 2
+  Allocating in stage 1
 ----------------------------------------------
 
-Logical Table ID in stage 2 was not supplied by table placement for table ecmp_group_table.
-Allocating Logical Table ID 0 in stage 2
-Allocating Table Type ID 0 of type exact in stage 2
+Logical Table ID in stage 1 was not supplied by table placement for table ecmp_group_table.
+Allocating Logical Table ID 0 in stage 1
+Allocating Table Type ID 0 of type exact in stage 1
 Match Overhead:
   Field --version_valid-- [3:0] (4 bits)
   Field --immediate-- [15:0] (16 bits)
@@ -1012,9 +975,9 @@
 Allocating: Byte 3 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ecmp_metadata.groupId[15:8]}.
 
 ---------------------------------------------
-Call to can_any_match_key_fields_be_shared(stage=2, table=ecmp_group_table)
+Call to can_any_match_key_fields_be_shared(stage=1, table=ecmp_group_table)
 ---------------------------------------------
-Decided way to allocate for table ecmp_group_table in stage 2 WAS non_shared
+Decided way to allocate for table ecmp_group_table in stage 1 WAS non_shared
 Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ecmp_metadata.selector[7:0]}.
 Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ecmp_metadata.selector[15:8]}.
 Allocating: Byte 2 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ecmp_metadata.groupId[7:0]}.
@@ -1139,12 +1102,12 @@
   Field right_rotate [3:0]   : 0x0   (4 bits in instruction bits [19:16])
   Field low_bit_hi [2:0]     : 0x0   (3 bits in instruction bits [22:20])
 
-Allocating Action ALU 2 (16 bits) in stage 2 for match table ecmp_group_table's action set_egress_port
-Allocating VLIW Instruction : 0 in stage 2 for match table ecmp_group_table's action set_egress_port
+Allocating Action ALU 2 (16 bits) in stage 1 for match table ecmp_group_table's action set_egress_port
+Allocating VLIW Instruction : 0 in stage 1 for match table ecmp_group_table's action set_egress_port
 
 ----------------------------------------------
 Call to Allocate P4 Table with table ingress_port_count_table__action__, number_entries = 1024, table id = None, and match type = exact
-  Allocating in stage 3
+  Allocating in stage 2
 ----------------------------------------------
 
 ram_size_matrix = 
@@ -1177,17 +1140,17 @@
 byte_enables = []
 After allocation of 32s, available_slots is []
 final packing is []
-Allocating Action Logical Table ID 0 in stage 3
+Allocating Action Logical Table ID 0 in stage 2
 
 ----------------------------------------------
-Call to Allocate P4 Table with table ingress_port_counter, number_entries = 254, table id = None, and match type = exact
-  Allocating in stage 3
+Call to Allocate P4 Table with table ingress_port_counter, number_entries = 510, table id = None, and match type = exact
+  Allocating in stage 2
 ----------------------------------------------
 
 stat_stage_table referenced: indirect
 stat Table Resource Request is:
 SRAM Resource Request for table ingress_port_counter (of type statistics), with 1 ways wants 2 rams.
-Sram Resource Request for P4 table ingress_port_counter with handle 67108865 of type statistics in stage 3
+Sram Resource Request for P4 table ingress_port_counter with handle 67108865 of type statistics in stage 2
   table_type : statistics
   rams_for_width : 1
   use_stash : False
@@ -1203,20 +1166,20 @@
 
 ----------------------------------------------
 Call to Allocate P4 Table with table ingress_port_count_table, number_entries = 1024, table id = None, and match type = exact
-  Allocating in stage 3
+  Allocating in stage 2
 ----------------------------------------------
 
-Logical Table ID in stage 3 was not supplied by table placement for table ingress_port_count_table.
-Allocating Logical Table ID 0 in stage 3
-Allocating Table Type ID 0 of type exact in stage 3
+Logical Table ID in stage 2 was not supplied by table placement for table ingress_port_count_table.
+Allocating Logical Table ID 0 in stage 2
+Allocating Table Type ID 0 of type exact in stage 2
 Match Overhead:
   Field --version_valid-- [3:0] (4 bits)
   Field --instruction_address-- [1:0] (2 bits)
   Field --statistics_pointer-- [19:0] (20 bits)
 
-Logical Table ID in stage 3 was not supplied by table placement for table ingress_port_count_table.
-Allocating Logical Table ID 0 in stage 3
-Allocating Table Type ID 0 of type exact in stage 3
+Logical Table ID in stage 2 was not supplied by table placement for table ingress_port_count_table.
+Allocating Logical Table ID 0 in stage 2
+Allocating Table Type ID 0 of type exact in stage 2
 Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
 Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
 Match Table Resource Request is:
@@ -1224,12 +1187,12 @@
 Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
 Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
 No micro instructions needed for action count_ingress executed from table ingress_port_count_table.
-Allocating Action ALU 0 (32 bits) in stage 3 for match table ingress_port_count_table's action count_ingress
-Allocating VLIW Instruction : 0 in stage 3 for match table ingress_port_count_table's action count_ingress
+Allocating Action ALU 0 (32 bits) in stage 2 for match table ingress_port_count_table's action count_ingress
+Allocating VLIW Instruction : 0 in stage 2 for match table ingress_port_count_table's action count_ingress
 
 ----------------------------------------------
 Call to Allocate P4 Table with table egress_port_count_table__action__, number_entries = 1024, table id = None, and match type = exact
-  Allocating in stage 3
+  Allocating in stage 2
 ----------------------------------------------
 
 ram_size_matrix = 
@@ -1262,17 +1225,17 @@
 byte_enables = []
 After allocation of 32s, available_slots is []
 final packing is []
-Allocating Action Logical Table ID 1 in stage 3
+Allocating Action Logical Table ID 1 in stage 2
 
 ----------------------------------------------
-Call to Allocate P4 Table with table egress_port_counter, number_entries = 254, table id = None, and match type = exact
-  Allocating in stage 3
+Call to Allocate P4 Table with table egress_port_counter, number_entries = 510, table id = None, and match type = exact
+  Allocating in stage 2
 ----------------------------------------------
 
 stat_stage_table referenced: indirect
 stat Table Resource Request is:
 SRAM Resource Request for table egress_port_counter (of type statistics), with 1 ways wants 2 rams.
-Sram Resource Request for P4 table egress_port_counter with handle 67108866 of type statistics in stage 3
+Sram Resource Request for P4 table egress_port_counter with handle 67108866 of type statistics in stage 2
   table_type : statistics
   rams_for_width : 1
   use_stash : False
@@ -1290,19 +1253,19 @@
 
 ----------------------------------------------
 Call to Allocate P4 Table with table egress_port_count_table, number_entries = 1024, table id = None, and match type = exact
-  Allocating in stage 3
+  Allocating in stage 2
 ----------------------------------------------
 
-Logical Table ID in stage 3 was not supplied by table placement for table egress_port_count_table.
-Allocating Logical Table ID 1 in stage 3
-Allocating Table Type ID 1 of type exact in stage 3
+Logical Table ID in stage 2 was not supplied by table placement for table egress_port_count_table.
+Allocating Logical Table ID 1 in stage 2
+Allocating Table Type ID 1 of type exact in stage 2
 Match Overhead:
   Field --version_valid-- [3:0] (4 bits)
   Field --statistics_pointer-- [19:0] (20 bits)
 
-Logical Table ID in stage 3 was not supplied by table placement for table egress_port_count_table.
-Allocating Logical Table ID 1 in stage 3
-Allocating Table Type ID 1 of type exact in stage 3
+Logical Table ID in stage 2 was not supplied by table placement for table egress_port_count_table.
+Allocating Logical Table ID 1 in stage 2
+Allocating Table Type ID 1 of type exact in stage 2
 Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
 Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
 Match Table Resource Request is:
@@ -1310,102 +1273,32 @@
 Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
 Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
 No micro instructions needed for action count_egress executed from table egress_port_count_table.
-Allocating Action ALU 0 (32 bits) in stage 3 for match table egress_port_count_table's action count_egress
-Allocating VLIW Instruction : 0 in stage 3 for match table egress_port_count_table's action count_egress
-
-----------------------------------------------
-Call to Allocate P4 Table with table egress_pkt__action__, number_entries = 1024, table id = None, and match type = exact
-  Allocating in stage 0
-----------------------------------------------
-
-ram_size_matrix = 
- (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
-       0              0              0               0                0               0                0                0        # 0
-
-immediate_size_matrix = 
- (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
-       0              0              0               0                0               0                0                0        # 0
-
-hash_to_phv_matrix = 
- (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
-       0              0              0               0                0               0                0                0        # 0
-
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
-  action add_packet_in_hdr has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
-  action add_packet_in_hdr has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
-  action add_packet_in_hdr has []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-Allocating Action Logical Table ID 1 in stage 0
-
-----------------------------------------------
-Call to Allocate P4 Table with table egress_pkt, number_entries = 1024, table id = None, and match type = exact
-  Allocating in stage 0
-----------------------------------------------
-
-Logical Table ID in stage 0 was not supplied by table placement for table egress_pkt.
-Allocating Logical Table ID 1 in stage 0
-Allocating Table Type ID 1 of type exact in stage 0
-Match Overhead:
-  Field --version_valid-- [3:0] (4 bits)
-  Field --instruction_address-- [1:0] (2 bits)
-
-Logical Table ID in stage 0 was not supplied by table placement for table egress_pkt.
-Allocating Logical Table ID 1 in stage 0
-Allocating Table Type ID 1 of type exact in stage 0
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.copy_to_cpu[0:0]}.
-Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
-Match Table Resource Request is:
-SRAM Resource Request for table egress_pkt (of type match), with 0 ways wants 0 rams.
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.copy_to_cpu[0:0]}.
-Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[5:0], --validity_check--packet_out_hdr[0:0], unused[0:0]}.
-For action add_packet_in_hdr, formed micro_instruction:
-Micro Instruction deposit-field for PHV Container 82 has bit width 20
-  Field Src2 [3:0]           : 0x2   (4 bits in instruction bits [3:0])
-  Field Src1 [4:0]           : 0x19   (5 bits in instruction bits [8:4])
-  Field Src1i [0:0]          : 0x0   (1 bits in instruction bits [9:9])
-  Field opcode [0:0]         : 0x1   (1 bits in instruction bits [10:10])
-  Field high_bit [2:0]       : 0x0   (3 bits in instruction bits [13:11])
-  Field low_bit_lo [1:0]     : 0x0   (2 bits in instruction bits [15:14])
-  Field right_rotate [2:0]   : 0x0   (3 bits in instruction bits [18:16])
-  Field low_bit_hi [0:0]     : 0x0   (1 bits in instruction bits [19:19])
-
-For action add_packet_in_hdr, formed micro_instruction:
-Micro Instruction deposit-field for PHV Container 145 has bit width 23
-  Field Src2 [3:0]           : 0x1   (4 bits in instruction bits [3:0])
-  Field Src1 [4:0]           : 0x0   (5 bits in instruction bits [8:4])
-  Field Src1i [0:0]          : 0x0   (1 bits in instruction bits [9:9])
-  Field opcode [0:0]         : 0x1   (1 bits in instruction bits [10:10])
-  Field high_bit [3:0]       : 0xf   (4 bits in instruction bits [14:11])
-  Field low_bit_lo [0:0]     : 0x1   (1 bits in instruction bits [15:15])
-  Field right_rotate [3:0]   : 0x9   (4 bits in instruction bits [19:16])
-  Field low_bit_hi [2:0]     : 0x3   (3 bits in instruction bits [22:20])
-
-Allocating Action ALU 18 (8 bits) in stage 0 for match table egress_pkt's action add_packet_in_hdr
-Allocating Action ALU 17 (16 bits) in stage 0 for match table egress_pkt's action add_packet_in_hdr
-Allocating VLIW Instruction : 0 in stage 0 for match table egress_pkt's action add_packet_in_hdr
+Allocating Action ALU 0 (32 bits) in stage 2 for match table egress_port_count_table's action count_egress
+Allocating VLIW Instruction : 0 in stage 2 for match table egress_port_count_table's action count_egress
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
 Cannot find table object for 'egress_port_count_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
 Cannot find table object for 'egress_port_count_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
 Cannot find table object for 'egress_port_count_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
 Cannot find table object for 'egress_port_count_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
 Cannot find table object for 'egress_port_count_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
 Cannot find table object for 'egress_port_count_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
 Cannot find table object for 'egress_port_count_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
 Cannot find table object for 'egress_port_count_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
 Cannot find table object for 'egress_port_count_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
 Cannot find table object for 'egress_port_count_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
+Cannot find table object for 'egress_port_count_table_always_true_condition'.
+Cannot find table object for 'process_packet_out_table_always_true_condition'.
 Skipping p4_primitive StageModifyFieldFromHashBitsPrimitive from overhead calculation.
 Action ecmp_group for table table0 cannot be used as a default action (table miss action).  The action requires the use of hash distribution, which is not available when a table misses.
 Field ig_intr_md_for_tm.ucast_egress_port not contiguous on gateway input