diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/montara/logs/mau.log b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/montara/logs/mau.log
index 3494ab0..b5a583e 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/montara/logs/mau.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/ecmp/montara/logs/mau.log
@@ -1,7 +1,7 @@
 +---------------------------------------------------------------------+
 |  Log file: mau.log                                                  |
 |  Compiler version: 5.1.0 (fca32d1)                                  |
-|  Created on: Tue Sep 12 11:16:41 2017                               |
+|  Created on: Wed Sep 13 01:00:26 2017                               |
 +---------------------------------------------------------------------+
 
 Match Table table0 did not specify the number of entries required. A default value (512) will be used.
@@ -21,129 +21,7 @@
 Match Entry Table table0 has already been associated with stat Table table0_counter.
 Match Entry Table ecmp_group_table has already been associated with stat Table ecmp_group_table_counter.
 Match table ingress_port_count_table has no match key fields
-Cannot use hash-action for table ingress_port_count_table with no key because the number of entries required by side-effect table ingress_port_counter is not a power of 2 -- 510.
-
-##########################################
-  Call to decide_action_data_placement(stage=0, table=ingress_port_count_table)
-##########################################
-
-
-Max immediate bits used in any action is 0 bits.
-Overhead bit width for table ingress_port_count_table is 22 bits.
-Bits available in overhead for non-essential immediate data is 32 bits.
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 0 bits in match overhead
-Overhead bit width for table ingress_port_count_table is 22 bits.
-Overhead SRAMs to use = 97
-  Entries requested = 1024  and match entries get = 0
-ram_size_matrix = 
- (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
-       0              0              0               0                0               0                0                0        # 0
-
-immediate_size_matrix = 
- (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
-       0              0              0               0                0               0                0                0        # 0
-
-hash_to_phv_matrix = 
- (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
-       0              0              0               0                0               0                0                0        # 0
-
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
-  action count_ingress has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
-  action count_ingress has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
-  action count_ingress has []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-Action Data SRAMs to use = 0
-TODO: Total RAMs use when put 0 bits in match overhead: 97
-TODO: Total RAMs use when put 0 bits in match overhead: 97
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 8 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 16 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 24 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 32 bits in match overhead
-
-##########################################
-
-Best Ram Usage is 97 rams
-Best Immediate placement is 0 bits
 Match table egress_port_count_table has no match key fields
-Cannot use hash-action for table egress_port_count_table with no key because the number of entries required by side-effect table egress_port_counter is not a power of 2 -- 510.
-
-##########################################
-  Call to decide_action_data_placement(stage=0, table=egress_port_count_table)
-##########################################
-
-
-Max immediate bits used in any action is 0 bits.
-Overhead bit width for table egress_port_count_table is 20 bits.
-Bits available in overhead for non-essential immediate data is 32 bits.
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 0 bits in match overhead
-Overhead bit width for table egress_port_count_table is 20 bits.
-Overhead SRAMs to use = 97
-  Entries requested = 1024  and match entries get = 0
-ram_size_matrix = 
- (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
-       0              0              0               0                0               0                0                0        # 0
-
-immediate_size_matrix = 
- (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
-       0              0              0               0                0               0                0                0        # 0
-
-hash_to_phv_matrix = 
- (8, 8, False)  (8, 8, True)  (8, 32, False)  (16, 16, False)  (16, 16, True)  (16, 32, False)  (32, 32, False)  (32, 32, True) 
-       0              0              0               0                0               0                0                0        # 0
-
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
-  action count_egress has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
-  action count_egress has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
-  action count_egress has []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-Action Data SRAMs to use = 0
-TODO: Total RAMs use when put 0 bits in match overhead: 97
-TODO: Total RAMs use when put 0 bits in match overhead: 97
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 8 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 16 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 24 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 32 bits in match overhead
-
-##########################################
-
-Best Ram Usage is 97 rams
-Best Immediate placement is 0 bits
 
 ##########################################
   Call to decide_action_data_placement(stage=0, table=process_packet_out_table)
@@ -515,8 +393,8 @@
 final packing is [(16, 0, False)]
 ----------------------------------------------
  Call to allocate_hash_distribution_units with
-    hash_algorithm = crc32
-    hash_output_width = 32
+    hash_algorithm = crc16
+    hash_output_width = 16
     hash_bits_need = 1
     output_hash_bit_start = 0
     immediate_bit_positions = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
@@ -525,17 +403,17 @@
 available_tuples_sorted_by_parity_bytes_available = [(0, 3, 0), (1, 3, 0)]
 available_tuples_split_sorted_by_parity_bytes_available = []
 Allocate fresh exact match group / hash group
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {udp.dstPort[7:0]}.
-Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {udp.dstPort[15:8]}.
-Allocating: Byte 2 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {udp.srcPort[7:0]}.
-Allocating: Byte 3 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {udp.srcPort[15:8]}.
-Allocating: Byte 4 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ipv4.dstAddr[7:0]}.
-Allocating: Byte 5 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ipv4.dstAddr[15:8]}.
-Allocating: Byte 6 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ipv4.dstAddr[23:16]}.
+Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ipv4.dstAddr[7:0]}.
+Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ipv4.dstAddr[15:8]}.
+Allocating: Byte 2 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ipv4.dstAddr[23:16]}.
+Allocating: Byte 3 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {tcp.dstPort[7:0]}.
+Allocating: Byte 4 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ipv4.srcAddr[31:24]}.
+Allocating: Byte 5 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {tcp.srcPort[7:0]}.
+Allocating: Byte 6 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {tcp.dstPort[15:8]}.
 Allocating: Byte 7 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ipv4.dstAddr[31:24]}.
-Allocating: Byte 8 is of type exact and member of group 0 (parity group 1) with 16 bytes. for {ipv4.srcAddr[31:24]}.
+Allocating: Byte 8 is of type exact and member of group 0 (parity group 1) with 16 bytes. for {ipv4.srcAddr[7:0]}.
 Allocating: Byte 9 is of type exact and member of group 0 (parity group 1) with 16 bytes. for {ipv4.srcAddr[15:8]}.
-Allocating: Byte 10 is of type exact and member of group 0 (parity group 1) with 16 bytes. for {ipv4.srcAddr[7:0]}.
+Allocating: Byte 10 is of type exact and member of group 0 (parity group 1) with 16 bytes. for {tcp.srcPort[15:8]}.
 Allocating: Byte 11 is of type exact and member of group 0 (parity group 1) with 16 bytes. for {ipv4.srcAddr[23:16]}.
 -------------------
 Call to _allocate_hash_distribution_and_hash_bits
@@ -548,10 +426,12 @@
 -------------------
 Allocating Hash Distribution Group 0/0 for table table0__action__ in stage 0.
 Allocating Hash Bit 0 in hash match group 0 for table table0__action__ in stage 0.
-seed = 0x7bd5c66f
-set the seed to be [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
+total_hash_result_bits = 16
+polynomial_as_hex_int = 0x18005
+seed = 0x0
+set the seed to be [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
 Hash Function 0
-hash_bit_0 = udp.dstPort[2] ^ udp.dstPort[8] ^ udp.dstPort[12] ^ udp.dstPort[14] ^ udp.dstPort[15] ^ udp.srcPort[0] ^ udp.srcPort[8] ^ udp.srcPort[9] ^ udp.srcPort[10] ^ udp.srcPort[11] ^ udp.srcPort[12] ^ udp.srcPort[14] ^ udp.srcPort[15] ^ ipv4.dstAddr[3] ^ ipv4.dstAddr[6] ^ ipv4.dstAddr[8] ^ ipv4.dstAddr[9] ^ ipv4.dstAddr[11] ^ ipv4.dstAddr[12] ^ ipv4.dstAddr[17] ^ ipv4.dstAddr[18] ^ ipv4.dstAddr[19] ^ ipv4.dstAddr[22] ^ ipv4.dstAddr[25] ^ ipv4.dstAddr[27] ^ ipv4.dstAddr[28] ^ ipv4.dstAddr[30] ^ ipv4.srcAddr[24] ^ ipv4.srcAddr[25] ^ ipv4.srcAddr[26] ^ ipv4.srcAddr[9] ^ ipv4.srcAddr[15] ^ ipv4.srcAddr[0] ^ ipv4.srcAddr[4] ^ ipv4.srcAddr[5] ^ ipv4.srcAddr[6] ^ ipv4.srcAddr[7] ^ ipv4.srcAddr[17] ^ ipv4.srcAddr[19] ^ ipv4.srcAddr[20] ^ ipv4.srcAddr[21] ^ ipv4.srcAddr[22] ^ ipv4.srcAddr[23] ^ 1
+hash_bit_0 = ipv4.dstAddr[0] ^ ipv4.dstAddr[1] ^ ipv4.dstAddr[2] ^ ipv4.dstAddr[3] ^ ipv4.dstAddr[4] ^ ipv4.dstAddr[5] ^ ipv4.dstAddr[6] ^ ipv4.dstAddr[7] ^ ipv4.dstAddr[8] ^ ipv4.dstAddr[9] ^ ipv4.dstAddr[10] ^ ipv4.dstAddr[11] ^ ipv4.dstAddr[13] ^ ipv4.dstAddr[15] ^ ipv4.dstAddr[17] ^ ipv4.dstAddr[18] ^ ipv4.dstAddr[19] ^ ipv4.dstAddr[20] ^ ipv4.dstAddr[21] ^ ipv4.dstAddr[22] ^ ipv4.dstAddr[23] ^ tcp.dstPort[0] ^ tcp.dstPort[1] ^ tcp.dstPort[2] ^ tcp.dstPort[3] ^ tcp.dstPort[4] ^ tcp.dstPort[5] ^ tcp.dstPort[6] ^ tcp.dstPort[7] ^ ipv4.srcAddr[24] ^ ipv4.srcAddr[25] ^ ipv4.srcAddr[26] ^ ipv4.srcAddr[27] ^ ipv4.srcAddr[28] ^ ipv4.srcAddr[29] ^ ipv4.srcAddr[30] ^ tcp.srcPort[0] ^ tcp.srcPort[1] ^ tcp.srcPort[2] ^ tcp.srcPort[3] ^ tcp.srcPort[4] ^ tcp.srcPort[5] ^ tcp.srcPort[6] ^ tcp.srcPort[7] ^ tcp.dstPort[8] ^ tcp.dstPort[9] ^ tcp.dstPort[11] ^ tcp.dstPort[12] ^ tcp.dstPort[13] ^ tcp.dstPort[14] ^ tcp.dstPort[15] ^ ipv4.dstAddr[24] ^ ipv4.dstAddr[25] ^ ipv4.dstAddr[26] ^ ipv4.dstAddr[27] ^ ipv4.dstAddr[28] ^ ipv4.srcAddr[0] ^ ipv4.srcAddr[1] ^ ipv4.srcAddr[3] ^ ipv4.srcAddr[4] ^ ipv4.srcAddr[5] ^ ipv4.srcAddr[6] ^ ipv4.srcAddr[7] ^ ipv4.srcAddr[8] ^ ipv4.srcAddr[9] ^ ipv4.srcAddr[10] ^ ipv4.srcAddr[11] ^ ipv4.srcAddr[12] ^ ipv4.srcAddr[13] ^ ipv4.srcAddr[15] ^ tcp.srcPort[8] ^ tcp.srcPort[9] ^ tcp.srcPort[10] ^ tcp.srcPort[13] ^ tcp.srcPort[14] ^ tcp.srcPort[15] ^ ipv4.srcAddr[17] ^ ipv4.srcAddr[18] ^ ipv4.srcAddr[21] ^ ipv4.srcAddr[22] ^ ipv4.srcAddr[23] ^ 0
 hash_bit_1 = 0
 hash_bit_2 = 0
 hash_bit_3 = 0
@@ -710,23 +590,23 @@
 Allocating Action ALU 2 (16 bits) in stage 0 for match table table0's action set_egress_port
 Allocating VLIW Instruction : 0 in stage 0 for match table table0's action set_egress_port
 For action ecmp_group, formed micro_instruction:
-Micro Instruction alu_a for PHV Container 134 has bit width 23
-  Field Src2 [3:0]     : 0x6   (4 bits in instruction bits [3:0])
+Micro Instruction alu_a for PHV Container 135 has bit width 23
+  Field Src2 [3:0]     : 0x7   (4 bits in instruction bits [3:0])
   Field Src1 [4:0]     : 0x0   (5 bits in instruction bits [8:4])
   Field Src1i [0:0]    : 0x1   (1 bits in instruction bits [9:9])
   Field opcode [9:0]   : 0x31e   (10 bits in instruction bits [19:10])
   Field unused [2:0]   : 0x0   (3 bits in instruction bits [22:20])
 
 For action ecmp_group, formed micro_instruction:
-Micro Instruction alu_a for PHV Container 135 has bit width 23
-  Field Src2 [3:0]     : 0x7   (4 bits in instruction bits [3:0])
+Micro Instruction alu_a for PHV Container 136 has bit width 23
+  Field Src2 [3:0]     : 0x8   (4 bits in instruction bits [3:0])
   Field Src1 [4:0]     : 0x2   (5 bits in instruction bits [8:4])
   Field Src1i [0:0]    : 0x1   (1 bits in instruction bits [9:9])
   Field opcode [9:0]   : 0x31e   (10 bits in instruction bits [19:10])
   Field unused [2:0]   : 0x0   (3 bits in instruction bits [22:20])
 
-Allocating Action ALU 6 (16 bits) in stage 0 for match table table0's action ecmp_group
 Allocating Action ALU 7 (16 bits) in stage 0 for match table table0's action ecmp_group
+Allocating Action ALU 8 (16 bits) in stage 0 for match table table0's action ecmp_group
 Allocating VLIW Instruction : 1 in stage 0 for match table table0's action ecmp_group
 For action send_to_cpu, formed micro_instruction:
 Micro Instruction deposit-field for PHV Container 130 has bit width 23
@@ -740,8 +620,8 @@
   Field low_bit_hi [2:0]     : 0x0   (3 bits in instruction bits [22:20])
 
 For action send_to_cpu, formed micro_instruction:
-Micro Instruction deposit-field for PHV Container 67 has bit width 20
-  Field Src2 [3:0]           : 0x3   (4 bits in instruction bits [3:0])
+Micro Instruction deposit-field for PHV Container 68 has bit width 20
+  Field Src2 [3:0]           : 0x4   (4 bits in instruction bits [3:0])
   Field Src1 [4:0]           : 0x19   (5 bits in instruction bits [8:4])
   Field Src1i [0:0]          : 0x0   (1 bits in instruction bits [9:9])
   Field opcode [0:0]         : 0x1   (1 bits in instruction bits [10:10])
@@ -762,12 +642,12 @@
   Field low_bit_hi [2:0]     : 0x3   (3 bits in instruction bits [22:20])
 
 Allocating Action ALU 2 (16 bits) in stage 0 for match table table0's action send_to_cpu
-Allocating Action ALU 3 (8 bits) in stage 0 for match table table0's action send_to_cpu
+Allocating Action ALU 4 (8 bits) in stage 0 for match table table0's action send_to_cpu
 Allocating Action ALU 1 (16 bits) in stage 0 for match table table0's action send_to_cpu
 Allocating VLIW Instruction : 1 in stage 0 for match table table0's action send_to_cpu
 For action _drop, formed micro_instruction:
-Micro Instruction deposit-field for PHV Container 68 has bit width 20
-  Field Src2 [3:0]           : 0x4   (4 bits in instruction bits [3:0])
+Micro Instruction deposit-field for PHV Container 69 has bit width 20
+  Field Src2 [3:0]           : 0x5   (4 bits in instruction bits [3:0])
   Field Src1 [4:0]           : 0x19   (5 bits in instruction bits [8:4])
   Field Src1i [0:0]          : 0x0   (1 bits in instruction bits [9:9])
   Field opcode [0:0]         : 0x1   (1 bits in instruction bits [10:10])
@@ -776,7 +656,7 @@
   Field right_rotate [2:0]   : 0x3   (3 bits in instruction bits [18:16])
   Field low_bit_hi [0:0]     : 0x1   (1 bits in instruction bits [19:19])
 
-Allocating Action ALU 4 (8 bits) in stage 0 for match table table0's action _drop
+Allocating Action ALU 5 (8 bits) in stage 0 for match table table0's action _drop
 Allocating VLIW Instruction : 2 in stage 0 for match table table0's action _drop
 Ternary table Pack Format = 
 Pack Format:
@@ -880,8 +760,8 @@
   Field low_bit_hi [2:0]     : 0x0   (3 bits in instruction bits [22:20])
 
 For action _process_packet_out, formed micro_instruction:
-Micro Instruction deposit-field for PHV Container 67 has bit width 20
-  Field Src2 [3:0]           : 0x3   (4 bits in instruction bits [3:0])
+Micro Instruction deposit-field for PHV Container 68 has bit width 20
+  Field Src2 [3:0]           : 0x4   (4 bits in instruction bits [3:0])
   Field Src1 [4:0]           : 0x18   (5 bits in instruction bits [8:4])
   Field Src1i [0:0]          : 0x0   (1 bits in instruction bits [9:9])
   Field opcode [0:0]         : 0x1   (1 bits in instruction bits [10:10])
@@ -891,7 +771,7 @@
   Field low_bit_hi [0:0]     : 0x0   (1 bits in instruction bits [19:19])
 
 Allocating Action ALU 2 (16 bits) in stage 0 for match table process_packet_out_table's action _process_packet_out
-Allocating Action ALU 3 (8 bits) in stage 0 for match table process_packet_out_table's action _process_packet_out
+Allocating Action ALU 4 (8 bits) in stage 0 for match table process_packet_out_table's action _process_packet_out
 Allocating VLIW Instruction : 2 in stage 0 for match table process_packet_out_table's action _process_packet_out
 
 ----------------------------------------------
@@ -1143,7 +1023,7 @@
 Allocating Action Logical Table ID 0 in stage 2
 
 ----------------------------------------------
-Call to Allocate P4 Table with table ingress_port_counter, number_entries = 510, table id = None, and match type = exact
+Call to Allocate P4 Table with table ingress_port_counter, number_entries = 512, table id = None, and match type = exact
   Allocating in stage 2
 ----------------------------------------------
 
@@ -1172,23 +1052,185 @@
 Logical Table ID in stage 2 was not supplied by table placement for table ingress_port_count_table.
 Allocating Logical Table ID 0 in stage 2
 Allocating Table Type ID 0 of type exact in stage 2
-Match Overhead:
-  Field --version_valid-- [3:0] (4 bits)
-  Field --instruction_address-- [1:0] (2 bits)
-  Field --statistics_pointer-- [19:0] (20 bits)
+Too few bits (9) specified to address ingress_port_counter from table ingress_port_count_table.  10 are needed.
+The most significant 1 bit will be padded with zeros.
+----------------------------------------------
+ Call to allocate_hash_distribution_units with
+    hash_algorithm = identity
+    hash_output_width = 10
+    hash_bits_need = 10
+    output_hash_bit_start = 0
+    immediate_bit_positions = None
+    used_for = Statistics Address
+----------------------------------------------
+available_tuples_sorted_by_parity_bytes_available = [(0, 3, 0), (1, 3, 0)]
+available_tuples_split_sorted_by_parity_bytes_available = []
+Allocate fresh exact match group / hash group
+Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md.ingress_port[7:0]}.
+Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md.ingress_port[8:8]}.
+-------------------
+Call to _allocate_hash_distribution_and_hash_bits
+    p4_table = ingress_port_count_table
+    used_for = Statistics Address
+    hash_distribution_hash_id = 0
+    hash_group_id = 0
+    hash_bits_in_units = OrderedDict([(0, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9])])
+    address_left_shift = 1
+-------------------
+Allocating Hash Distribution Group 0/0 for table ingress_port_count_table in stage 2.
+Allocating Hash Bit 0 in hash match group 0 for table ingress_port_count_table in stage 2.
+Allocating Hash Bit 1 in hash match group 0 for table ingress_port_count_table in stage 2.
+Allocating Hash Bit 2 in hash match group 0 for table ingress_port_count_table in stage 2.
+Allocating Hash Bit 3 in hash match group 0 for table ingress_port_count_table in stage 2.
+Allocating Hash Bit 4 in hash match group 0 for table ingress_port_count_table in stage 2.
+Allocating Hash Bit 5 in hash match group 0 for table ingress_port_count_table in stage 2.
+Allocating Hash Bit 6 in hash match group 0 for table ingress_port_count_table in stage 2.
+Allocating Hash Bit 7 in hash match group 0 for table ingress_port_count_table in stage 2.
+Allocating Hash Bit 8 in hash match group 0 for table ingress_port_count_table in stage 2.
+Allocating Hash Bit 9 in hash match group 0 for table ingress_port_count_table in stage 2.
+seed = 0x0
+set the seed to be [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
+Hash Function 0
+hash_bit_0 = ig_intr_md.ingress_port[0] ^ 0
+hash_bit_1 = ig_intr_md.ingress_port[1] ^ 0
+hash_bit_2 = ig_intr_md.ingress_port[2] ^ 0
+hash_bit_3 = ig_intr_md.ingress_port[3] ^ 0
+hash_bit_4 = ig_intr_md.ingress_port[4] ^ 0
+hash_bit_5 = ig_intr_md.ingress_port[5] ^ 0
+hash_bit_6 = ig_intr_md.ingress_port[6] ^ 0
+hash_bit_7 = ig_intr_md.ingress_port[7] ^ 0
+hash_bit_8 = ig_intr_md.ingress_port[8] ^ 0
+hash_bit_9 = 0
+hash_bit_10 = 0
+hash_bit_11 = 0
+hash_bit_12 = 0
+hash_bit_13 = 0
+hash_bit_14 = 0
+hash_bit_15 = 0
+hash_bit_16 = 0
+hash_bit_17 = 0
+hash_bit_18 = 0
+hash_bit_19 = 0
+hash_bit_20 = 0
+hash_bit_21 = 0
+hash_bit_22 = 0
+hash_bit_23 = 0
+hash_bit_24 = 0
+hash_bit_25 = 0
+hash_bit_26 = 0
+hash_bit_27 = 0
+hash_bit_28 = 0
+hash_bit_29 = 0
+hash_bit_30 = 0
+hash_bit_31 = 0
+hash_bit_32 = 0
+hash_bit_33 = 0
+hash_bit_34 = 0
+hash_bit_35 = 0
+hash_bit_36 = 0
+hash_bit_37 = 0
+hash_bit_38 = 0
+hash_bit_39 = 0
+hash_bit_40 = 0
+hash_bit_41 = 0
+hash_bit_42 = 0
+hash_bit_43 = 0
+hash_bit_44 = 0
+hash_bit_45 = 0
+hash_bit_46 = 0
+hash_bit_47 = 0
+hash_bit_48 = 0
+hash_bit_49 = 0
+hash_bit_50 = 0
+hash_bit_51 = 0
 
-Logical Table ID in stage 2 was not supplied by table placement for table ingress_port_count_table.
-Allocating Logical Table ID 0 in stage 2
-Allocating Table Type ID 0 of type exact in stage 2
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
-Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
+Allocating: Byte 2 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
+Allocating: Byte 3 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
 Match Table Resource Request is:
 SRAM Resource Request for table ingress_port_count_table (of type match), with 0 ways wants 0 rams.
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
-Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
+Allocating: Byte 2 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
+Allocating: Byte 3 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
 No micro instructions needed for action count_ingress executed from table ingress_port_count_table.
 Allocating Action ALU 0 (32 bits) in stage 2 for match table ingress_port_count_table's action count_ingress
 Allocating VLIW Instruction : 0 in stage 2 for match table ingress_port_count_table's action count_ingress
+My hash-action stage table is 
+StageHashActionTable
+  stage_number: 2
+  number_entries 1024
+  pack_format:
+    Pack Format:
+  table_word_width: 0
+  memory_word_width: 0
+  entries_per_table_word: 0
+  number_memory_units_per_table_word: 0
+  entry_list: [
+]
+
+  p4_table: 'ingress_port_count_table'
+  stage_table_handle: 0
+  stage_table_type_handle: 0
+  stage_gateway_table: StageGatewayTable
+  stage_number: 2
+  number_entries 0
+  memory_resource_allocation GatewayMemoryResourceAllocation:
+  memory_type: gateway
+  memory_units: [[15]]
+  home_row: -1
+  stateful_action_bus_output: None
+
+  p4_table: '_condition_2'
+
+  match_group_resource_allocation:
+  vliw_resource_allocation:
+   action handle 536870914 maps to:
+VliwResourceAllocation:
+  match_table_name: ingress_port_count_table
+  p4_action: count_ingress
+  address_to_use: 1
+  full_address: 64
+  vliw_instruction_number: 0
+  color: 0
+  direction: ingress
+  micro_instructions:
+
+  action_to_vliw_mapping:
+    action handle 536870914 maps to vliw instruction 0, color 0, and direction ingress and is found in instruction address 1
+  hash_distribution_usages:
+    MAU Hash Distribution Resource Usage for P4 table ingress_port_count_table
+  exact_match_group_resource_allocation : HashMatchGroupResourceAllocation:
+  match_groups: [(0, 16)]
+  match_group_key_bit_width: 9
+  match_group_phv_bit_scrambling: OrderedDict([(('ig_intr_md.ingress_port', 0), 0), (('ig_intr_md.ingress_port', 1), 1), (('ig_intr_md.ingress_port', 2), 2), (('ig_intr_md.ingress_port', 3), 3), (('ig_intr_md.ingress_port', 4), 4), (('ig_intr_md.ingress_port', 5), 5), (('ig_intr_md.ingress_port', 6), 6), (('ig_intr_md.ingress_port', 7), 7), (('ig_intr_md.ingress_port', 8), 8)])
+    ('ig_intr_md.ingress_port', 0) -> 0
+    ('ig_intr_md.ingress_port', 1) -> 1
+    ('ig_intr_md.ingress_port', 2) -> 2
+    ('ig_intr_md.ingress_port', 3) -> 3
+    ('ig_intr_md.ingress_port', 4) -> 4
+    ('ig_intr_md.ingress_port', 5) -> 5
+    ('ig_intr_md.ingress_port', 6) -> 6
+    ('ig_intr_md.ingress_port', 7) -> 7
+    ('ig_intr_md.ingress_port', 8) -> 8
+  hash_function_dictionary: OrderedDict([(0, <p4c_tofino.target.tofino.llir.mau.stage.resources.hash_function.HashFunction object at 0x7f1960def790>)])
+  hash_group_id: 0
+  seed: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
+  table_direction: ingress
+
+  hash_distribution_resource_allocations :
+Hash Distribution:
+  source_hash_group : 0
+  hash_distribution_hash_id : 0
+  hash_distribution_group_id : 0
+  hash_distribution_used_for : Statistics Address
+  table_direction : ingress
+  bits_to_use : [0, 1, 2, 3, 4, 5, 6, 7, 8, 9]
+  left_shift : 1
+  expanded_lo : False
+  expanded_hi : False
+  expanded_bit_width : 0
+  immediate_position : unused
+
+
+
 
 ----------------------------------------------
 Call to Allocate P4 Table with table egress_port_count_table__action__, number_entries = 1024, table id = None, and match type = exact
@@ -1228,7 +1270,7 @@
 Allocating Action Logical Table ID 1 in stage 2
 
 ----------------------------------------------
-Call to Allocate P4 Table with table egress_port_counter, number_entries = 510, table id = None, and match type = exact
+Call to Allocate P4 Table with table egress_port_counter, number_entries = 512, table id = None, and match type = exact
   Allocating in stage 2
 ----------------------------------------------
 
@@ -1248,8 +1290,8 @@
       ram_word_select_bits : 0
       ram_enable_select_bits : 0
 
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
-Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
+Allocating: Byte 2 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
+Allocating: Byte 3 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
 
 ----------------------------------------------
 Call to Allocate P4 Table with table egress_port_count_table, number_entries = 1024, table id = None, and match type = exact
@@ -1259,22 +1301,185 @@
 Logical Table ID in stage 2 was not supplied by table placement for table egress_port_count_table.
 Allocating Logical Table ID 1 in stage 2
 Allocating Table Type ID 1 of type exact in stage 2
-Match Overhead:
-  Field --version_valid-- [3:0] (4 bits)
-  Field --statistics_pointer-- [19:0] (20 bits)
+Too few bits (9) specified to address egress_port_counter from table egress_port_count_table.  10 are needed.
+The most significant 1 bit will be padded with zeros.
+----------------------------------------------
+ Call to allocate_hash_distribution_units with
+    hash_algorithm = identity
+    hash_output_width = 10
+    hash_bits_need = 10
+    output_hash_bit_start = 0
+    immediate_bit_positions = None
+    used_for = Statistics Address
+----------------------------------------------
+available_tuples_sorted_by_parity_bytes_available = [(1, 3, 0), (0, 2, 4)]
+available_tuples_split_sorted_by_parity_bytes_available = []
+Allocate fresh exact match group / hash group
+Allocating: Byte 8 is of type exact and member of group 0 (parity group 1) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
+Allocating: Byte 9 is of type exact and member of group 0 (parity group 1) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
+-------------------
+Call to _allocate_hash_distribution_and_hash_bits
+    p4_table = egress_port_count_table
+    used_for = Statistics Address
+    hash_distribution_hash_id = 1
+    hash_group_id = 1
+    hash_bits_in_units = OrderedDict([(0, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9])])
+    address_left_shift = 1
+-------------------
+Allocating Hash Distribution Group 1/0 for table egress_port_count_table in stage 2.
+Allocating Hash Bit 0 in hash match group 1 for table egress_port_count_table in stage 2.
+Allocating Hash Bit 1 in hash match group 1 for table egress_port_count_table in stage 2.
+Allocating Hash Bit 2 in hash match group 1 for table egress_port_count_table in stage 2.
+Allocating Hash Bit 3 in hash match group 1 for table egress_port_count_table in stage 2.
+Allocating Hash Bit 4 in hash match group 1 for table egress_port_count_table in stage 2.
+Allocating Hash Bit 5 in hash match group 1 for table egress_port_count_table in stage 2.
+Allocating Hash Bit 6 in hash match group 1 for table egress_port_count_table in stage 2.
+Allocating Hash Bit 7 in hash match group 1 for table egress_port_count_table in stage 2.
+Allocating Hash Bit 8 in hash match group 1 for table egress_port_count_table in stage 2.
+Allocating Hash Bit 9 in hash match group 1 for table egress_port_count_table in stage 2.
+seed = 0x0
+set the seed to be [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
+Hash Function 0
+hash_bit_0 = ig_intr_md_for_tm.ucast_egress_port[0] ^ 0
+hash_bit_1 = ig_intr_md_for_tm.ucast_egress_port[1] ^ 0
+hash_bit_2 = ig_intr_md_for_tm.ucast_egress_port[2] ^ 0
+hash_bit_3 = ig_intr_md_for_tm.ucast_egress_port[3] ^ 0
+hash_bit_4 = ig_intr_md_for_tm.ucast_egress_port[4] ^ 0
+hash_bit_5 = ig_intr_md_for_tm.ucast_egress_port[5] ^ 0
+hash_bit_6 = ig_intr_md_for_tm.ucast_egress_port[6] ^ 0
+hash_bit_7 = ig_intr_md_for_tm.ucast_egress_port[7] ^ 0
+hash_bit_8 = ig_intr_md_for_tm.ucast_egress_port[8] ^ 0
+hash_bit_9 = 0
+hash_bit_10 = 0
+hash_bit_11 = 0
+hash_bit_12 = 0
+hash_bit_13 = 0
+hash_bit_14 = 0
+hash_bit_15 = 0
+hash_bit_16 = 0
+hash_bit_17 = 0
+hash_bit_18 = 0
+hash_bit_19 = 0
+hash_bit_20 = 0
+hash_bit_21 = 0
+hash_bit_22 = 0
+hash_bit_23 = 0
+hash_bit_24 = 0
+hash_bit_25 = 0
+hash_bit_26 = 0
+hash_bit_27 = 0
+hash_bit_28 = 0
+hash_bit_29 = 0
+hash_bit_30 = 0
+hash_bit_31 = 0
+hash_bit_32 = 0
+hash_bit_33 = 0
+hash_bit_34 = 0
+hash_bit_35 = 0
+hash_bit_36 = 0
+hash_bit_37 = 0
+hash_bit_38 = 0
+hash_bit_39 = 0
+hash_bit_40 = 0
+hash_bit_41 = 0
+hash_bit_42 = 0
+hash_bit_43 = 0
+hash_bit_44 = 0
+hash_bit_45 = 0
+hash_bit_46 = 0
+hash_bit_47 = 0
+hash_bit_48 = 0
+hash_bit_49 = 0
+hash_bit_50 = 0
+hash_bit_51 = 0
 
-Logical Table ID in stage 2 was not supplied by table placement for table egress_port_count_table.
-Allocating Logical Table ID 1 in stage 2
-Allocating Table Type ID 1 of type exact in stage 2
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
-Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
+Allocating: Byte 2 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
+Allocating: Byte 3 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
 Match Table Resource Request is:
 SRAM Resource Request for table egress_port_count_table (of type match), with 0 ways wants 0 rams.
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
-Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
+Allocating: Byte 2 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
+Allocating: Byte 3 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
 No micro instructions needed for action count_egress executed from table egress_port_count_table.
 Allocating Action ALU 0 (32 bits) in stage 2 for match table egress_port_count_table's action count_egress
 Allocating VLIW Instruction : 0 in stage 2 for match table egress_port_count_table's action count_egress
+My hash-action stage table is 
+StageHashActionTable
+  stage_number: 2
+  number_entries 1024
+  pack_format:
+    Pack Format:
+  table_word_width: 0
+  memory_word_width: 0
+  entries_per_table_word: 0
+  number_memory_units_per_table_word: 0
+  entry_list: [
+]
+
+  p4_table: 'egress_port_count_table'
+  stage_table_handle: 1
+  stage_table_type_handle: 1
+  stage_gateway_table: StageGatewayTable
+  stage_number: 2
+  number_entries 0
+  memory_resource_allocation GatewayMemoryResourceAllocation:
+  memory_type: gateway
+  memory_units: [[14]]
+  home_row: -1
+  stateful_action_bus_output: None
+
+  p4_table: 'egress_port_count_table_always_true_condition'
+
+  match_group_resource_allocation:
+  vliw_resource_allocation:
+   action handle 536870916 maps to:
+VliwResourceAllocation:
+  match_table_name: egress_port_count_table
+  p4_action: count_egress
+  address_to_use: 0
+  full_address: 64
+  vliw_instruction_number: 0
+  color: 0
+  direction: ingress
+  micro_instructions:
+
+  action_to_vliw_mapping:
+    action handle 536870916 maps to vliw instruction 0, color 0, and direction ingress and is found in instruction address 0
+  hash_distribution_usages:
+    MAU Hash Distribution Resource Usage for P4 table egress_port_count_table
+  exact_match_group_resource_allocation : HashMatchGroupResourceAllocation:
+  match_groups: [(0, 16)]
+  match_group_key_bit_width: 73
+  match_group_phv_bit_scrambling: OrderedDict([(('ig_intr_md_for_tm.ucast_egress_port', 0), 64), (('ig_intr_md_for_tm.ucast_egress_port', 1), 65), (('ig_intr_md_for_tm.ucast_egress_port', 2), 66), (('ig_intr_md_for_tm.ucast_egress_port', 3), 67), (('ig_intr_md_for_tm.ucast_egress_port', 4), 68), (('ig_intr_md_for_tm.ucast_egress_port', 5), 69), (('ig_intr_md_for_tm.ucast_egress_port', 6), 70), (('ig_intr_md_for_tm.ucast_egress_port', 7), 71), (('ig_intr_md_for_tm.ucast_egress_port', 8), 72)])
+    ('ig_intr_md_for_tm.ucast_egress_port', 0) -> 64
+    ('ig_intr_md_for_tm.ucast_egress_port', 1) -> 65
+    ('ig_intr_md_for_tm.ucast_egress_port', 2) -> 66
+    ('ig_intr_md_for_tm.ucast_egress_port', 3) -> 67
+    ('ig_intr_md_for_tm.ucast_egress_port', 4) -> 68
+    ('ig_intr_md_for_tm.ucast_egress_port', 5) -> 69
+    ('ig_intr_md_for_tm.ucast_egress_port', 6) -> 70
+    ('ig_intr_md_for_tm.ucast_egress_port', 7) -> 71
+    ('ig_intr_md_for_tm.ucast_egress_port', 8) -> 72
+  hash_function_dictionary: OrderedDict([(0, <p4c_tofino.target.tofino.llir.mau.stage.resources.hash_function.HashFunction object at 0x7f1960df4450>)])
+  hash_group_id: 1
+  seed: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
+  table_direction: ingress
+
+  hash_distribution_resource_allocations :
+Hash Distribution:
+  source_hash_group : 1
+  hash_distribution_hash_id : 1
+  hash_distribution_group_id : 0
+  hash_distribution_used_for : Statistics Address
+  table_direction : ingress
+  bits_to_use : [0, 1, 2, 3, 4, 5, 6, 7, 8, 9]
+  left_shift : 1
+  expanded_lo : False
+  expanded_hi : False
+  expanded_bit_width : 0
+  immediate_position : unused
+
+
+
 Cannot find table object for 'process_packet_out_table_always_true_condition'.
 Cannot find table object for 'process_packet_out_table_always_true_condition'.
 Cannot find table object for 'egress_port_count_table_always_true_condition'.