Workaround to counter-issue as suggested by Antonin
Manually modified via makefile context.json
Change-Id: Ibed9e0691bf1d552db28470da57955e8f3ca802a
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/context/context.json b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/context/context.json
index 4c129d7..4450ef9 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/context/context.json
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/context/context.json
@@ -1,5 +1,5 @@
{
- "build_date": "Fri Sep 8 08:24:46 2017",
+ "build_date": "Wed Sep 13 00:59:11 2017",
"phv_allocation": [
{
"ingress": [
@@ -17229,12 +17229,13 @@
"actions": [
{
"p4_parameters": [],
+ "disallowed_as_default_action_reason": "USES_HASH_DIST",
"handle": 536870914,
"name": "count_ingress",
"indirect_resources": [],
"override_stat_full_addr": 0,
"override_meter_addr_pfe": false,
- "allowed_as_default_action": true,
+ "allowed_as_default_action": false,
"override_stat_addr_pfe": true,
"override_stateful_addr_pfe": false,
"override_meter_full_addr": 0,
@@ -17264,12 +17265,13 @@
"actions": [
{
"p4_parameters": [],
+ "disallowed_as_default_action_reason": "USES_HASH_DIST",
"handle": 536870914,
"name": "count_ingress",
"indirect_resources": [],
"override_stat_full_addr": 0,
"override_meter_addr_pfe": false,
- "allowed_as_default_action": true,
+ "allowed_as_default_action": false,
"override_stat_addr_pfe": true,
"override_stateful_addr_pfe": false,
"override_meter_full_addr": 0,
@@ -17302,18 +17304,24 @@
"pack_format": [
{
"memory_word_width": 0,
- "entries_per_table_word": 1,
+ "entries_per_table_word": 0,
"table_word_width": 0,
"number_memory_units_per_table_word": 0
}
],
+ "hash_functions": [
+ {
+ "hash_function_number": 0,
+ "hash_bits": []
+ }
+ ],
"result_physical_buses": [
1
],
"logical_table_id": 0,
"stage_number": 1,
"stage_table_type": "match_with_no_key",
- "size": 1
+ "size": 1024
}
],
"match_type": "match_with_no_key"
@@ -17366,12 +17374,13 @@
"actions": [
{
"p4_parameters": [],
+ "disallowed_as_default_action_reason": "USES_HASH_DIST",
"handle": 536870916,
"name": "count_egress",
"indirect_resources": [],
"override_stat_full_addr": 0,
"override_meter_addr_pfe": false,
- "allowed_as_default_action": true,
+ "allowed_as_default_action": false,
"override_stat_addr_pfe": true,
"override_stateful_addr_pfe": false,
"override_meter_full_addr": 0,
@@ -17401,12 +17410,13 @@
"actions": [
{
"p4_parameters": [],
+ "disallowed_as_default_action_reason": "USES_HASH_DIST",
"handle": 536870916,
"name": "count_egress",
"indirect_resources": [],
"override_stat_full_addr": 0,
"override_meter_addr_pfe": false,
- "allowed_as_default_action": true,
+ "allowed_as_default_action": false,
"override_stat_addr_pfe": true,
"override_stateful_addr_pfe": false,
"override_meter_full_addr": 0,
@@ -17439,18 +17449,24 @@
"pack_format": [
{
"memory_word_width": 0,
- "entries_per_table_word": 1,
+ "entries_per_table_word": 0,
"table_word_width": 0,
"number_memory_units_per_table_word": 0
}
],
+ "hash_functions": [
+ {
+ "hash_function_number": 0,
+ "hash_bits": []
+ }
+ ],
"result_physical_buses": [
0
],
"logical_table_id": 1,
"stage_number": 1,
"stage_table_type": "match_with_no_key",
- "size": 1
+ "size": 1024
}
],
"match_type": "match_with_no_key"
@@ -18386,7 +18402,7 @@
"packet_counter_resolution": 32,
"pfe_bit_position": 19,
"how_referenced": "indirect",
- "size": 510
+ "size": 512
},
{
"direction": "ingress",
@@ -18429,7 +18445,7 @@
"packet_counter_resolution": 32,
"pfe_bit_position": 19,
"how_referenced": "indirect",
- "size": 510
+ "size": 512
},
{
"direction": "ingress",
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/context/mau.context.json b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/context/mau.context.json
index df27a61..1ace548 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/context/mau.context.json
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/context/mau.context.json
@@ -1,14 +1,137 @@
{
"ProgramInfo": {
"ProgramName": "default",
- "BuildDate": "Fri Sep 8 08:24:46 2017",
+ "BuildDate": "Wed Sep 13 00:59:11 2017",
"CompilerVersion": "5.1.0"
},
"HashJsonNode": {
- "TableCount": 0,
+ "TableCount": 2,
"ProxyTables": {},
- "AllTables": {},
- "HashFieldCount": 0
+ "AllTables": {
+ "ingress_port_count_table": {
+ "1": [
+ {
+ "0": [
+ {},
+ {
+ "seed": 0
+ }
+ ],
+ "1": [
+ {},
+ {
+ "seed": 0
+ }
+ ],
+ "2": [
+ {},
+ {
+ "seed": 0
+ }
+ ],
+ "3": [
+ {},
+ {
+ "seed": 0
+ }
+ ],
+ "4": [
+ {},
+ {
+ "seed": 0
+ }
+ ],
+ "5": [
+ {},
+ {
+ "seed": 0
+ }
+ ],
+ "6": [
+ {},
+ {
+ "seed": 0
+ }
+ ],
+ "7": [
+ {},
+ {
+ "seed": 0
+ }
+ ],
+ "8": [
+ {},
+ {
+ "seed": 0
+ }
+ ]
+ }
+ ],
+ "Handle": 16777217
+ },
+ "egress_port_count_table": {
+ "1": [
+ {
+ "0": [
+ {},
+ {
+ "seed": 0
+ }
+ ],
+ "1": [
+ {},
+ {
+ "seed": 0
+ }
+ ],
+ "2": [
+ {},
+ {
+ "seed": 0
+ }
+ ],
+ "3": [
+ {},
+ {
+ "seed": 0
+ }
+ ],
+ "4": [
+ {},
+ {
+ "seed": 0
+ }
+ ],
+ "5": [
+ {},
+ {
+ "seed": 0
+ }
+ ],
+ "6": [
+ {},
+ {
+ "seed": 0
+ }
+ ],
+ "7": [
+ {},
+ {
+ "seed": 0
+ }
+ ],
+ "8": [
+ {},
+ {
+ "seed": 0
+ }
+ ]
+ }
+ ],
+ "Handle": 16777218
+ }
+ },
+ "HashFieldCount": 2
},
"EntryFormatNode": {
"ExmEntryFormat": {
@@ -16664,21 +16787,16 @@
"stage_tables": [
{
"stage_number": 1,
- "stage_table_type": "match_with_no_key",
- "number_entries": 1,
+ "stage_table_type": "hash_action",
+ "number_entries": 1024,
"pack_format_length": 1,
"pack_format": [
{
"table_word_width": 0,
"memory_word_width": 0,
- "entries_per_table_word": 1,
+ "entries_per_table_word": 0,
"number_memory_units_per_table_word": 0,
- "entry_list": [
- {
- "entry_number": 0,
- "field_list": []
- }
- ]
+ "entry_list": []
}
],
"memory_resource_allocation": null,
@@ -16715,15 +16833,15 @@
],
"match_group_key_bit_width": 16,
"match_group_phv_bit_scrambling": {
- "ig_intr_md_for_tm.ucast_egress_port[0]": 0,
- "ig_intr_md_for_tm.ucast_egress_port[1]": 1,
- "ig_intr_md_for_tm.ucast_egress_port[2]": 2,
- "ig_intr_md_for_tm.ucast_egress_port[3]": 3,
- "ig_intr_md_for_tm.ucast_egress_port[4]": 4,
- "ig_intr_md_for_tm.ucast_egress_port[5]": 5,
- "ig_intr_md_for_tm.ucast_egress_port[6]": 6,
- "ig_intr_md_for_tm.ucast_egress_port[7]": 7,
- "ig_intr_md_for_tm.ucast_egress_port[8]": 8
+ "ig_intr_md_for_tm.ucast_egress_port[0]": 16,
+ "ig_intr_md_for_tm.ucast_egress_port[1]": 17,
+ "ig_intr_md_for_tm.ucast_egress_port[2]": 18,
+ "ig_intr_md_for_tm.ucast_egress_port[3]": 19,
+ "ig_intr_md_for_tm.ucast_egress_port[4]": 20,
+ "ig_intr_md_for_tm.ucast_egress_port[5]": 21,
+ "ig_intr_md_for_tm.ucast_egress_port[6]": 22,
+ "ig_intr_md_for_tm.ucast_egress_port[7]": 23,
+ "ig_intr_md_for_tm.ucast_egress_port[8]": 24
},
"match_group_match_bit_scrambling": {},
"seed": [
@@ -16829,8 +16947,8 @@
{
"name": "count_ingress",
"handle": 536870914,
- "allowed_to_be_default_action": true,
- "disallowed_as_default_action_reason": null,
+ "allowed_to_be_default_action": false,
+ "disallowed_as_default_action_reason": "USES_HASH_DIST",
"override_stat_addr_pfe": true,
"override_stat_addr": false,
"override_stat_full_addr": 0,
@@ -16861,8 +16979,8 @@
"default_action": {
"name": "count_ingress",
"handle": 536870914,
- "allowed_to_be_default_action": true,
- "disallowed_as_default_action_reason": null,
+ "allowed_to_be_default_action": false,
+ "disallowed_as_default_action_reason": "USES_HASH_DIST",
"override_stat_addr_pfe": true,
"override_stat_addr": false,
"override_stat_full_addr": 0,
@@ -16902,7 +17020,7 @@
"p4_stateful_tables": [],
"p4_selection_tables": [],
"include_idletime": false,
- "performs_hash_action": false,
+ "performs_hash_action": true,
"uses_range": false,
"number_entries_with_ranges": 0,
"uses_versioning": true,
@@ -16923,21 +17041,16 @@
"stage_tables": [
{
"stage_number": 1,
- "stage_table_type": "match_with_no_key",
- "number_entries": 1,
+ "stage_table_type": "hash_action",
+ "number_entries": 1024,
"pack_format_length": 1,
"pack_format": [
{
"table_word_width": 0,
"memory_word_width": 0,
- "entries_per_table_word": 1,
+ "entries_per_table_word": 0,
"number_memory_units_per_table_word": 0,
- "entry_list": [
- {
- "entry_number": 0,
- "field_list": []
- }
- ]
+ "entry_list": []
}
],
"memory_resource_allocation": null,
@@ -17070,8 +17183,8 @@
{
"name": "count_egress",
"handle": 536870916,
- "allowed_to_be_default_action": true,
- "disallowed_as_default_action_reason": null,
+ "allowed_to_be_default_action": false,
+ "disallowed_as_default_action_reason": "USES_HASH_DIST",
"override_stat_addr_pfe": true,
"override_stat_addr": false,
"override_stat_full_addr": 0,
@@ -17102,8 +17215,8 @@
"default_action": {
"name": "count_egress",
"handle": 536870916,
- "allowed_to_be_default_action": true,
- "disallowed_as_default_action_reason": null,
+ "allowed_to_be_default_action": false,
+ "disallowed_as_default_action_reason": "USES_HASH_DIST",
"override_stat_addr_pfe": true,
"override_stat_addr": false,
"override_stat_full_addr": 0,
@@ -17143,7 +17256,7 @@
"p4_stateful_tables": [],
"p4_selection_tables": [],
"include_idletime": false,
- "performs_hash_action": false,
+ "performs_hash_action": true,
"uses_range": false,
"number_entries_with_ranges": 0,
"uses_versioning": true,
@@ -18534,7 +18647,7 @@
"name": "ingress_port_counter",
"handle": 67108865,
"direction": "ingress",
- "number_entries": 510,
+ "number_entries": 512,
"stage_tables_length": 1,
"stage_tables": [
{
@@ -18642,7 +18755,7 @@
"name": "egress_port_counter",
"handle": 67108866,
"direction": "ingress",
- "number_entries": 510,
+ "number_entries": 512,
"stage_tables_length": 1,
"stage_tables": [
{
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/default.json b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/default.json
index d082348..0141a65 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/default.json
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/default.json
@@ -9,10 +9,8 @@
"name" : "scalars_0",
"id" : 0,
"fields" : [
- ["tmp_0", 104, false],
- ["tmp", 8, false],
- ["tmp_1", 32, false],
- ["tmp_2", 32, false]
+ ["tmp", 32, false],
+ ["tmp_0", 32, false]
]
},
{
@@ -194,7 +192,7 @@
"parser_ops" : [],
"transitions" : [
{
- "value" : "0xff",
+ "value" : "0x00ff",
"mask" : null,
"next_state" : "parse_pkt_out"
},
@@ -381,50 +379,10 @@
{
"name" : "start",
"id" : 7,
- "parser_ops" : [
- {
- "parameters" : [
- {
- "type" : "field",
- "value" : ["scalars", "tmp_0"]
- },
- {
- "type" : "lookahead",
- "value" : [0, 104]
- }
- ],
- "op" : "set"
- },
- {
- "parameters" : [
- {
- "type" : "field",
- "value" : ["scalars", "tmp"]
- },
- {
- "type" : "expression",
- "value" : {
- "type" : "expression",
- "value" : {
- "op" : "&",
- "left" : {
- "type" : "field",
- "value" : ["scalars", "tmp_0"]
- },
- "right" : {
- "type" : "hexstr",
- "value" : "0xff"
- }
- }
- }
- }
- ],
- "op" : "set"
- }
- ],
+ "parser_ops" : [],
"transitions" : [
{
- "value" : "0x00",
+ "value" : "0x00ff",
"mask" : null,
"next_state" : "parse_pkt_in"
},
@@ -437,7 +395,7 @@
"transition_key" : [
{
"type" : "field",
- "value" : ["scalars", "tmp"]
+ "value" : ["ig_intr_md", "egress_spec"]
}
]
}
@@ -650,7 +608,7 @@
"parameters" : [
{
"type" : "field",
- "value" : ["scalars", "tmp_1"]
+ "value" : ["scalars", "tmp"]
},
{
"type" : "expression",
@@ -680,7 +638,7 @@
},
{
"type" : "field",
- "value" : ["scalars", "tmp_1"]
+ "value" : ["scalars", "tmp"]
}
],
"source_info" : {
@@ -702,7 +660,7 @@
"parameters" : [
{
"type" : "field",
- "value" : ["scalars", "tmp_2"]
+ "value" : ["scalars", "tmp_0"]
},
{
"type" : "expression",
@@ -732,7 +690,7 @@
},
{
"type" : "field",
- "value" : ["scalars", "tmp_2"]
+ "value" : ["scalars", "tmp_0"]
}
],
"source_info" : {
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/asm.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/asm.log
index 45374d2..3c40129 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/asm.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/asm.log
@@ -1,6 +1,6 @@
+---------------------------------------------------------------------+
| Log file: asm.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Fri Sep 8 08:24:30 2017 |
+| Created on: Wed Sep 13 00:58:56 2017 |
+---------------------------------------------------------------------+
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.characterize.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.characterize.log
index 891b532..02d1e5c 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.characterize.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.characterize.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: mau.characterize.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Fri Sep 8 08:24:30 2017 |
+| Created on: Wed Sep 13 00:58:56 2017 |
+---------------------------------------------------------------------+
Match+Action Resource Usage
@@ -20,8 +20,8 @@
| process_packet_out_table | ingress | 0 | | - | 0 (0/0/0/0/0) | 0 | 1024 / 1 (-1023) | 0 / 0 (0) | 0 | 0 | 0/0/0/0/0/0/0/0 | 0 / 0 (0) | 0 / 0 (0) | 0 / 0 (0) | 0 | 0 / 0 (0) | 0 in 0 (0) | 1 in 0 (0) | - / - | - / - | - / - |
| stage 0 totals | - | - | - | - | 3 (0/0/2/0/1) | 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| | | | | | | | | | | | | | | | | | | | | | |
-| ingress_port_count_table | ingress | 1 | | - | 2 (0/0/2/0/0) | 0 | 1024 / 1 (-1023) | 0 / 0 (0) | 0 | 0 | 0/0/0/0/0/0/0/0 | 0 / 0 (0) | 0 / 0 (0) | 0 / 0 (0) | 0 | 0 / 0 (0) | 0 in 0 (0) | 1 in 0 (0) | - / - | - / - | - / - |
-| egress_port_count_table | ingress | 1 | | - | 2 (0/0/2/0/0) | 0 | 1024 / 1 (-1023) | 0 / 0 (0) | 0 | 0 | 0/0/0/0/0/0/0/0 | 0 / 0 (0) | 0 / 0 (0) | 0 / 0 (0) | 0 | 0 / 0 (0) | 0 in 0 (0) | 1 in 0 (0) | - / - | - / - | - / - |
+| ingress_port_count_table | ingress | 1 | | - | 2 (0/0/2/0/0) | 0 | 1024 / 1024 (0) | 0 / 0 (0) | 0 | 0 | 0/0/0/0/0/0/0/0 | 0 / 0 (0) | 0 / 0 (0) | 0 / 0 (0) | 0 | 0 / 0 (0) | 0 in 0 (0) | 0 in 0 (0) | - / - | - / - | - / - |
+| egress_port_count_table | ingress | 1 | | - | 2 (0/0/2/0/0) | 0 | 1024 / 1024 (0) | 0 / 0 (0) | 0 | 0 | 0/0/0/0/0/0/0/0 | 0 / 0 (0) | 0 / 0 (0) | 0 / 0 (0) | 0 | 0 / 0 (0) | 0 in 0 (0) | 0 in 0 (0) | - / - | - / - | - / - |
| stage 1 totals | - | - | - | - | 4 (0/0/4/0/0) | 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| | | | | | | | | | | | | | | | | | | | | | |
| overall totals | - | - | - | - | 7 (0/0/6/0/1) | 3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.config.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.config.log
index 81dcf25..e6c99a9 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.config.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.config.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: mau.config.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Fri Sep 8 08:24:30 2017 |
+| Created on: Wed Sep 13 00:58:56 2017 |
+---------------------------------------------------------------------+
Final Stage dependencies are:
@@ -709,26 +709,26 @@
Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x1 (previous_value=0x0 OR new_value=0x1).
Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x0 OR new value = 0x1)
Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 18.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 0 to come from 16-bit PHV container 2.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_address to be 18.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=2].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 2 to come from 16-bit PHV container 2.
That PHV byte contains {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 18.
-Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_enable to be 1.
-Configuring match input crossbar byte 1 to come from 16-bit PHV container 2.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_address to be 18.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=3].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 3 to come from 16-bit PHV container 2.
That PHV byte contains {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x4. (previous value = 0x0 OR new value = 0x4)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x0 OR new value = 0x1)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=40].byte1 to be 0x1.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=41].byte0 to be 0x1.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=42].byte0 to be 0x2.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=43].byte0 to be 0x4.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=44].byte0 to be 0x8.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=45].byte0 to be 0x10.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=46].byte0 to be 0x20.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=47].byte0 to be 0x40.
-Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=48].byte0 to be 0x80.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=40].byte1 to be 0x1.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=41].byte0 to be 0x1.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=42].byte0 to be 0x2.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=43].byte0 to be 0x4.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=44].byte0 to be 0x8.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=45].byte0 to be 0x10.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=46].byte0 to be 0x20.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=47].byte0 to be 0x40.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=1][hash_bit_index=48].byte0 to be 0x80.
Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x0 OR new value = 0x1)
Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_select to be 0.
Configuring rams.array.row[row=7].vh_xbar[search_bus_index=0].exactmatch_row_vh_xbar_ctl.exactmatch_row_vh_xbar_enable to be 1.
@@ -746,23 +746,23 @@
Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][0] to be 0xffffffff
Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[3][1] to be 0xffffffff
Configuring rams.array.row[7].gateway_table[1].gateway_table_ctl.gateway_table_mode to be 0x2
-Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xffffff
-Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xffff3f
+Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][0] to be 0xffff00
+Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[3][1] to be 0xffff00
Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0x8
Configuring rams.match.merge.gateway_next_table_lut[0][3] to be 0x11
Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[2].gateway_table_entry_versionvalid0 to be 0x3
Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[2].gateway_table_entry_versionvalid1 to be 0x3
Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[2][0] to be 0xffffffff
Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[2][1] to be 0xffffffff
-Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][0] to be 0xffffff
-Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][1] to be 0xff7fff
+Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][0] to be 0xff00ff
+Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[2][1] to be 0xff00ff
Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0xc (previous value 0x8 OR new value 0x4)
Configuring rams.match.merge.gateway_next_table_lut[0][2] to be 0x11
Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[1].gateway_table_entry_versionvalid0 to be 0x3
Configuring rams.array.row[7].gateway_table[1].gateway_table_vv_entry[1].gateway_table_entry_versionvalid1 to be 0x3
Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[1][0] to be 0xffffffff
Configuring rams.array.row[7].gateway_table[1].gateway_table_entry_matchdata[1][1] to be 0xffffffff
-Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][0] to be 0x1ffff
+Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][0] to be 0x3ffff
Configuring rams.array.row[7].gateway_table[1].gateway_table_data_entry[1][1] to be 0xffff
Configuring rams.match.merge.gateway_inhibit_lut[0] to be 0xe (previous value 0xc OR new value 0x2)
Configuring rams.match.merge.gateway_next_table_lut[0][1] to be 0x11
@@ -788,7 +788,7 @@
+------------------------------------------------------------------------
| Working on table ingress_port_count_table in stage 1 ---
+------------------------------------------------------------------------
---> Match Table with no key ingress_port_count_table with logical_table_id 0
+--> Hash Action Table ingress_port_count_table with logical_table_id 0
allocated_result_bus = Ram Data Bus MatchResult2R 0 left_and_right is 83 bits
Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x1 (previous_value=0x1 OR new_value=0x1).
Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x1 (previous_value=0x1 OR new_value=0x1).
@@ -808,6 +808,37 @@
Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x1 (previous_value=0x0 OR new_value=0x1).
Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=0].mau_action_instruction_adr_map_data to be 0x2000.
Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=0][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
+
+---- Hash Distribution Units for table ingress_port_count_table ----
+Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x1 OR new value = 0x1)
+Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_address to be 16.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=0].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 0 to come from 16-bit PHV container 0.
+ That PHV byte contains {ig_intr_md.ingress_port[7:0]}.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_address to be 16.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=1].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 1 to come from 16-bit PHV container 0.
+ That PHV byte contains {unused[6:0], ig_intr_md.ingress_port[8:8]}.
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x5. (previous value = 0x4 OR new value = 0x1)
+Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x1 OR new value = 0x1)
+Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=0].byte0 to be 0x1.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=1].byte0 to be 0x2.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=2].byte0 to be 0x4.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=3].byte0 to be 0x8.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=4].byte0 to be 0x10.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=5].byte0 to be 0x20.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=6].byte0 to be 0x40.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=7].byte0 to be 0x80.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=0][hash_bit_index=8].byte1 to be 0x1.
+Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1)
+Configuring rams.match.merge.mau_hash_group_config.hash_group_enable to be 1. (old value = 0 OR new value = 1).
+Configuring rams.match.merge.mau_hash_group_config.hash_group_sel to be 8. (old value = 0 OR new value = 8).
+Configuring rams.match.merge.mau_hash_group_config.hash_group_ctl to be 1. (old value = 0 OR new value = 1).
+Configuring rams.match.merge.mau_hash_group_shiftcount.mau_hash_group_shiftcount to be 0x1. (old value = 0x0 OR new value = 0x1).
+Configuring rams.match.merge.mau_hash_group_mask[which_16=0].mau_hash_group_mask to be 0x3ff. (previous value = 0x0 OR new value = 0x3ff)
+Configuring rams.match.merge.mau_hash_group_xbar_ctl[output_type_index=3][control_group_index=0].mau_hash_group_xbar_ctl to be 0x8 (old value = 0x0 OR new value = 0x8).
Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].stats_adr_payload_shifter_en to be 1.
Configuring rams.match.merge.mau_payload_shifter_enable[table_type=0][result_bus=1].action_instruction_adr_payload_shifter_en to be 1.
@@ -819,7 +850,7 @@
+------------------------------------------------------------------------
| Working on table egress_port_count_table in stage 1 ---
+------------------------------------------------------------------------
---> Match Table with no key egress_port_count_table with logical_table_id 1
+--> Hash Action Table egress_port_count_table with logical_table_id 1
allocated_result_bus = Ram Data Bus MatchResult1R 0 left_and_right is 83 bits
Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x1 OR new_value=0x2).
Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x1 OR new_value=0x2).
@@ -839,6 +870,37 @@
Configuring rams.match.merge.mau_action_instruction_adr_map_en[table_type_index=0].mau_action_instruction_adr_map_en to be 0x3 (previous_value=0x1 OR new_value=0x2).
Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=0].mau_action_instruction_adr_map_data to be 0x40.
Configuring rams.match.merge.mau_action_instruction_adr_map_data[table_type_index=0][logical_table=1][entry_index=1].mau_action_instruction_adr_map_data to be 0x0.
+
+---- Hash Distribution Units for table egress_port_count_table ----
+Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x3. (old value = 0x1 OR new value = 0x2)
+Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=8].match_input_xbar_816b_ctl_address to be 18.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=8].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 8 to come from 16-bit PHV container 2.
+ That PHV byte contains {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_address to be 18.
+Configuring dp.xbar_hash.xbar.match_input_xbar_816b_ctl[word_group=0][output_byte=9].match_input_xbar_816b_ctl_enable to be 1.
+Configuring match input crossbar byte 9 to come from 16-bit PHV container 2.
+ That PHV byte contains {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
+Configuring dp.match_input_xbar_din_power_ctl[14_byte_group=0][byte_position=8].match_input_xbar_din_power_ctl to be 0x5. (previous value = 0x5 OR new value = 0x4)
+Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=1][byte_number=0].parity_group_mask to be 0x2. (previous value = 0x0 OR new value = 0x2)
+Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=1][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=0].byte0 to be 0x1.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=1].byte0 to be 0x2.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=2].byte0 to be 0x4.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=3].byte0 to be 0x8.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=4].byte0 to be 0x10.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=5].byte0 to be 0x20.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=6].byte0 to be 0x40.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=7].byte0 to be 0x80.
+Configuring dp.xbar_hash.hash.galois_field_matrix[byte_pair_index=4][hash_bit_index=8].byte1 to be 0x1.
+Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x3. (previous value = 0x1 OR new value = 0x2)
+Configuring rams.match.merge.mau_hash_group_config.hash_group_enable to be 9. (old value = 1 OR new value = 8).
+Configuring rams.match.merge.mau_hash_group_config.hash_group_sel to be 152. (old value = 8 OR new value = 144).
+Configuring rams.match.merge.mau_hash_group_config.hash_group_ctl to be 65. (old value = 1 OR new value = 64).
+Configuring rams.match.merge.mau_hash_group_shiftcount.mau_hash_group_shiftcount to be 0x201. (old value = 0x1 OR new value = 0x200).
+Configuring rams.match.merge.mau_hash_group_mask[which_16=3].mau_hash_group_mask to be 0x3ff. (previous value = 0x0 OR new value = 0x3ff)
+Configuring rams.match.merge.mau_hash_group_xbar_ctl[output_type_index=3][control_group_index=0].mau_hash_group_xbar_ctl to be 0xb8 (old value = 0x8 OR new value = 0xb0).
--> Stage Gateway Table for condition egress_port_count_table_always_true_condition in stage 1
Configuring rams.match.merge.predication_ctl[direction_index=0].table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
Configuring rams.match.adrdist.adr_dist_table_thread[direction_index=0][copy_index=0].adr_dist_table_thread to be 0x3 (previous_value=0x3 OR new_value=0x2).
@@ -846,11 +908,11 @@
Configuring rams.match.merge.logical_table_thread[copy_index=0].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
Configuring rams.match.merge.logical_table_thread[copy_index=1].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
Configuring rams.match.merge.logical_table_thread[copy_index=2].logical_table_thread_ingress to be 0x3 (previous_value=0x3 OR new_value=0x2).
-Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x1. (old value = 0x1 OR new value = 0x0)
+Configuring dp.mau_match_input_xbar_exact_match_enable[direction_index=0].mau_match_input_xbar_exact_match_enable to be 0x3. (old value = 0x3 OR new value = 0x0)
Configuring dp.xbar_hash.xbar.mau_match_input_xbar_ternary_match_enable[direction_index=0].mau_match_input_xbar_ternary_match_enable to be 0x0. (old value = 0x0 OR new value = 0x0)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=0].parity_group_mask to be 0x1. (previous value = 0x1 OR new value = 0x0)
Configuring dp.xbar_hash.hash.parity_group_mask[parity_group_mask_index=0][byte_number=1].parity_group_mask to be 0x0. (previous value = 0x0 OR new value = 0x0)
-Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x1. (previous value = 0x1 OR new value = 0x1)
+Configuring dp.hashout_ctl.hash_group_ingress_enable to be 0x3. (previous value = 0x3 OR new value = 0x1)
Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data0_select to be 0x1
Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_data1_select to be 0x0
Configuring rams.array.row[7].gateway_table[0].gateway_table_ctl.gateway_table_input_hash0_select to be 0x1
@@ -1948,7 +2010,7 @@
Configuring dp.phv_fifo_enable.phv_fifo_egress_final_output_enable to be 0.
+------------------------------------------------------------------------
-| Number of configuration field values set in Match-Action Stages: 1567
+| Number of configuration field values set in Match-Action Stages: 1617
+------------------------------------------------------------------------
+------------------------------------------------------------------------
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.gateway.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.gateway.log
index 30897dd..2a1b0c2 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.gateway.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.gateway.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: mau.gateway.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Fri Sep 8 08:24:30 2017 |
+| Created on: Wed Sep 13 00:58:56 2017 |
+---------------------------------------------------------------------+
@@ -752,7 +752,7 @@
Gateway 14
------- Phase 0 -------------
Looking at gateway table 14
-match_groups_attached_to_gateway = OrderedDict([(0, (0, [0], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7f555b613450>, 0)])), (1, (None, [], None, [], []))])
+match_groups_attached_to_gateway = OrderedDict([(0, (0, [0], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7ff9ed740390>, 0)])), (1, (None, [], None, [], []))])
Search bus 0 on row 7
----------------------------
Trying to place Gateway Resource Request for table process_packet_out_table_always_true_condition needs access to 0 input bits in exact match group 0 (parity groups [0]) and hash group 0 for gateway 14.
@@ -1121,7 +1121,7 @@
Gateway 14
------- Phase 0 -------------
Looking at gateway table 14
-match_groups_attached_to_gateway = OrderedDict([(0, (0, [0], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7f555b192810>, 0)])), (1, (None, [], None, [], []))])
+match_groups_attached_to_gateway = OrderedDict([(0, (0, [0], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7ff9ed9d1790>, 0)])), (1, (None, [], None, [], []))])
Search bus 0 on row 7
----------------------------
Trying to place Gateway Resource Request for table process_packet_out_table_always_true_condition needs access to 0 input bits in exact match group 0 (parity groups [0]) and hash group 0 for gateway 14.
@@ -1495,15 +1495,15 @@
[42] = None
[43] = None
Hash Bit Mapping:
- (1, 0) --> 40
- (0, 0) --> 41
- (0, 1) --> 42
- (0, 2) --> 43
- (0, 3) --> 44
- (0, 4) --> 45
- (0, 5) --> 46
- (0, 6) --> 47
- (0, 7) --> 48
+ (3, 0) --> 40
+ (2, 0) --> 41
+ (2, 1) --> 42
+ (2, 2) --> 43
+ (2, 3) --> 44
+ (2, 4) --> 45
+ (2, 5) --> 46
+ (2, 6) --> 47
+ (2, 7) --> 48
Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 1 for gateway
Allocating: Gateway 15 in stage 1 for _condition_2.
@@ -1742,15 +1742,15 @@
[42] = None
[43] = None
Hash Bit Mapping:
- (1, 0) --> 40
- (0, 0) --> 41
- (0, 1) --> 42
- (0, 2) --> 43
- (0, 3) --> 44
- (0, 4) --> 45
- (0, 5) --> 46
- (0, 6) --> 47
- (0, 7) --> 48
+ (3, 0) --> 40
+ (2, 0) --> 41
+ (2, 1) --> 42
+ (2, 2) --> 43
+ (2, 3) --> 44
+ (2, 4) --> 45
+ (2, 5) --> 46
+ (2, 6) --> 47
+ (2, 7) --> 48
Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 1 for gateway
Allocating: Gateway 15 in stage 1 for _condition_2.
@@ -1846,7 +1846,7 @@
match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
Search bus 0 on row 7
- final_parity_group_ids = [(0, []), (1, [])]
+ final_parity_group_ids = [(0, [0]), (1, [])]
open_parity_group_ids = [0, 1]
----------------------------
@@ -1989,15 +1989,15 @@
[42] = None
[43] = None
Hash Bit Mapping:
- (1, 0) --> 40
- (0, 0) --> 41
- (0, 1) --> 42
- (0, 2) --> 43
- (0, 3) --> 44
- (0, 4) --> 45
- (0, 5) --> 46
- (0, 6) --> 47
- (0, 7) --> 48
+ (3, 0) --> 40
+ (2, 0) --> 41
+ (2, 1) --> 42
+ (2, 2) --> 43
+ (2, 3) --> 44
+ (2, 4) --> 45
+ (2, 5) --> 46
+ (2, 6) --> 47
+ (2, 7) --> 48
Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 1 for gateway
Allocating: Gateway 15 in stage 1 for _condition_2.
@@ -2106,7 +2106,7 @@
match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
Search bus 0 on row 7
- final_parity_group_ids = [(0, []), (1, [])]
+ final_parity_group_ids = [(0, [0]), (1, [])]
open_parity_group_ids = [0, 1]
----------------------------
@@ -2249,15 +2249,15 @@
[42] = None
[43] = None
Hash Bit Mapping:
- (1, 0) --> 40
- (0, 0) --> 41
- (0, 1) --> 42
- (0, 2) --> 43
- (0, 3) --> 44
- (0, 4) --> 45
- (0, 5) --> 46
- (0, 6) --> 47
- (0, 7) --> 48
+ (3, 0) --> 40
+ (2, 0) --> 41
+ (2, 1) --> 42
+ (2, 2) --> 43
+ (2, 3) --> 44
+ (2, 4) --> 45
+ (2, 5) --> 46
+ (2, 6) --> 47
+ (2, 7) --> 48
Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 1 for gateway
Allocating: Gateway 15 in stage 1 for _condition_2.
@@ -2279,7 +2279,7 @@
Gateway 14
------- Phase 0 -------------
Looking at gateway table 14
-match_groups_attached_to_gateway = OrderedDict([(0, (0, [0], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7f555f79cc90>, 0)])), (1, (None, [], None, [], []))])
+match_groups_attached_to_gateway = OrderedDict([(0, (0, [0], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7ff9f1742c50>, 0)])), (1, (None, [], None, [], []))])
Search bus 0 on row 7
----------------------------
Trying to place Gateway Resource Request for table egress_port_count_table_always_true_condition needs access to 0 input bits in exact match group 0 (parity groups [0]) and hash group 0 for gateway 14.
@@ -2491,7 +2491,7 @@
match_groups_attached_to_gateway = OrderedDict([(0, (None, [], None, [], [])), (1, (None, [], None, [], []))])
Search bus 0 on row 7
- final_parity_group_ids = [(0, []), (1, [])]
+ final_parity_group_ids = [(0, [0]), (1, [])]
open_parity_group_ids = [0, 1]
----------------------------
@@ -2634,15 +2634,15 @@
[42] = None
[43] = None
Hash Bit Mapping:
- (1, 0) --> 40
- (0, 0) --> 41
- (0, 1) --> 42
- (0, 2) --> 43
- (0, 3) --> 44
- (0, 4) --> 45
- (0, 5) --> 46
- (0, 6) --> 47
- (0, 7) --> 48
+ (3, 0) --> 40
+ (2, 0) --> 41
+ (2, 1) --> 42
+ (2, 2) --> 43
+ (2, 3) --> 44
+ (2, 4) --> 45
+ (2, 5) --> 46
+ (2, 6) --> 47
+ (2, 7) --> 48
Allocating: Ram Data Bus MatchSearch1 7 left_and_right is 128 bits in stage 1 for gateway
Allocating: Gateway 15 in stage 1 for _condition_2.
@@ -2664,7 +2664,7 @@
Gateway 14
------- Phase 0 -------------
Looking at gateway table 14
-match_groups_attached_to_gateway = OrderedDict([(0, (0, [0], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7f555b5fadd0>, 0)])), (1, (None, [], None, [], []))])
+match_groups_attached_to_gateway = OrderedDict([(0, (0, [0], 0, [0], [(<p4c_tofino.target.tofino.device.pipeline.mau.match_keys.packed_gateway_key.PackedGatewayKey object at 0x7ff9ed76bd10>, 0)])), (1, (None, [], None, [], []))])
Search bus 0 on row 7
----------------------------
Trying to place Gateway Resource Request for table egress_port_count_table_always_true_condition needs access to 0 input bits in exact match group 0 (parity groups [0]) and hash group 0 for gateway 14.
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.gw.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.gw.log
index e208fa4..f7b547f 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.gw.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.gw.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: mau.gw.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Fri Sep 8 08:24:30 2017 |
+| Created on: Wed Sep 13 00:58:56 2017 |
+---------------------------------------------------------------------+
cond _condition_0: not valid packet_out_hdr
@@ -10,13 +10,13 @@
cond _condition_0 can be gateway (1+0)x1
cond !_condition_0 can be gateway (1+0)x1
_condition_0 is gateway for table0
-cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 510
- ig_intr_md_for_tm.ucast_egress_port < 510
- ! ig_intr_md_for_tm.ucast_egress_port >= 510
+cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 512
+ ig_intr_md_for_tm.ucast_egress_port < 512
+ ! ig_intr_md_for_tm.ucast_egress_port >= 512
cond _condition_2 can be gateway (9+0)x1
cond !_condition_2 can be gateway (9+0)x1
_condition_2 is gateway for ingress_port_count_table
-fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f555fea6d90>]) and and xor_fields is OrderedSet()
+fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7ff9f1e46d10>]) and and xor_fields is OrderedSet()
fields = OrderedSet() and and xor_fields is OrderedSet()
cond _condition_0: not valid packet_out_hdr
not valid packet_out_hdr
@@ -24,13 +24,13 @@
cond _condition_0 can be gateway (1+0)x1
cond !_condition_0 can be gateway (1+0)x1
_condition_0 is gateway for table0
-cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 510
- ig_intr_md_for_tm.ucast_egress_port < 510
- ! ig_intr_md_for_tm.ucast_egress_port >= 510
+cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 512
+ ig_intr_md_for_tm.ucast_egress_port < 512
+ ! ig_intr_md_for_tm.ucast_egress_port >= 512
cond _condition_2 can be gateway (9+0)x1
cond !_condition_2 can be gateway (9+0)x1
_condition_2 is gateway for ingress_port_count_table
-fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f555fea6d90>]) and and xor_fields is OrderedSet()
+fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7ff9f1e46d10>]) and and xor_fields is OrderedSet()
fields = OrderedSet() and and xor_fields is OrderedSet()
cond _condition_0: not valid packet_out_hdr
not valid packet_out_hdr
@@ -38,13 +38,13 @@
cond _condition_0 can be gateway (1+0)x1
cond !_condition_0 can be gateway (1+0)x1
_condition_0 is gateway for table0
-cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 510
- ig_intr_md_for_tm.ucast_egress_port < 510
- ! ig_intr_md_for_tm.ucast_egress_port >= 510
+cond _condition_2: ig_intr_md_for_tm.ucast_egress_port < 512
+ ig_intr_md_for_tm.ucast_egress_port < 512
+ ! ig_intr_md_for_tm.ucast_egress_port >= 512
cond _condition_2 can be gateway (9+0)x1
cond !_condition_2 can be gateway (9+0)x1
_condition_2 is gateway for ingress_port_count_table
-fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7f555fea6d90>]) and and xor_fields is OrderedSet()
+fields = OrderedSet([<p4_hlir.hlir.p4_headers.p4_field object at 0x7ff9f1e46d10>]) and and xor_fields is OrderedSet()
fields = OrderedSet() and and xor_fields is OrderedSet()
cond _always_true: True == True
True
@@ -66,12 +66,12 @@
final.tcam: [(match=0 mask=0 T)], miss=False
--> Stage Gateway Table for condition _condition_2 in stage 1
T -> ingress_port_count_table(16), F -> None(255)
-building tcam for GatewayTest('ig_intr_md_for_tm.ucast_egress_port < 510')
- adding line (range=[ffff ffff 3fff] match=0 mask=0 T)
- adding line (range=[ffff 7fff ffff] match=0 mask=0 T)
- adding line (range=[1 ffff ffff] match=0 mask=0 T)
-tcam data: [(range=[ffff ffff 3fff] match=0 mask=0 T), (range=[ffff 7fff ffff] match=0 mask=0 T), (range=[1 ffff ffff] match=0 mask=0 T)]
-final.tcam: [(range=[ffff ffff 3fff] match=0 mask=0 T), (range=[ffff 7fff ffff] match=0 mask=0 T), (range=[1 ffff ffff] match=0 mask=0 T)], miss=False
+building tcam for GatewayTest('ig_intr_md_for_tm.ucast_egress_port < 512')
+ adding line (range=[ffff ffff 0] match=0 mask=0 T)
+ adding line (range=[ffff 0 ffff] match=0 mask=0 T)
+ adding line (range=[3 ffff ffff] match=0 mask=0 T)
+tcam data: [(range=[ffff ffff 0] match=0 mask=0 T), (range=[ffff 0 ffff] match=0 mask=0 T), (range=[3 ffff ffff] match=0 mask=0 T)]
+final.tcam: [(range=[ffff ffff 0] match=0 mask=0 T), (range=[ffff 0 ffff] match=0 mask=0 T), (range=[3 ffff ffff] match=0 mask=0 T)], miss=False
--> Stage Gateway Table for condition egress_port_count_table_always_true_condition in stage 1
T -> egress_port_count_table(17), F -> egress_port_count_table(17)
building tcam for GatewayTest('True')
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.log
index 8e46412..7cf0b8d 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: mau.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Fri Sep 8 08:24:30 2017 |
+| Created on: Wed Sep 13 00:58:56 2017 |
+---------------------------------------------------------------------+
Match Table table0 did not specify the number of entries required. A default value (512) will be used.
@@ -15,129 +15,7 @@
Metadata bridge_ingress_intrinsic containers added between ingress/egress: [128]
Match Entry Table table0 has already been associated with stat Table table0_counter.
Match table ingress_port_count_table has no match key fields
-Cannot use hash-action for table ingress_port_count_table with no key because the number of entries required by side-effect table ingress_port_counter is not a power of 2 -- 510.
-
-##########################################
- Call to decide_action_data_placement(stage=0, table=ingress_port_count_table)
-##########################################
-
-
-Max immediate bits used in any action is 0 bits.
-Overhead bit width for table ingress_port_count_table is 22 bits.
-Bits available in overhead for non-essential immediate data is 32 bits.
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 0 bits in match overhead
-Overhead bit width for table ingress_port_count_table is 22 bits.
-Overhead SRAMs to use = 97
- Entries requested = 1024 and match entries get = 0
-ram_size_matrix =
- (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
- 0 0 0 0 0 0 0 0 # 0
-
-immediate_size_matrix =
- (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
- 0 0 0 0 0 0 0 0 # 0
-
-hash_to_phv_matrix =
- (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
- 0 0 0 0 0 0 0 0 # 0
-
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
- action count_ingress has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
- action count_ingress has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
- action count_ingress has []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-Action Data SRAMs to use = 0
-TODO: Total RAMs use when put 0 bits in match overhead: 97
-TODO: Total RAMs use when put 0 bits in match overhead: 97
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 8 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 16 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 24 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 32 bits in match overhead
-
-##########################################
-
-Best Ram Usage is 97 rams
-Best Immediate placement is 0 bits
Match table egress_port_count_table has no match key fields
-Cannot use hash-action for table egress_port_count_table with no key because the number of entries required by side-effect table egress_port_counter is not a power of 2 -- 510.
-
-##########################################
- Call to decide_action_data_placement(stage=0, table=egress_port_count_table)
-##########################################
-
-
-Max immediate bits used in any action is 0 bits.
-Overhead bit width for table egress_port_count_table is 20 bits.
-Bits available in overhead for non-essential immediate data is 32 bits.
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 0 bits in match overhead
-Overhead bit width for table egress_port_count_table is 20 bits.
-Overhead SRAMs to use = 97
- Entries requested = 1024 and match entries get = 0
-ram_size_matrix =
- (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
- 0 0 0 0 0 0 0 0 # 0
-
-immediate_size_matrix =
- (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
- 0 0 0 0 0 0 0 0 # 0
-
-hash_to_phv_matrix =
- (8, 8, False) (8, 8, True) (8, 32, False) (16, 16, False) (16, 16, True) (16, 32, False) (32, 32, False) (32, 32, True)
- 0 0 0 0 0 0 0 0 # 0
-
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
- action count_egress has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
- action count_egress has []
-total action ram packing size = [0, 0, 0]
-action_ram_packing:
- action count_egress has []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-byte_enables = []
-After allocation of 32s, available_slots is []
-final packing is []
-Action Data SRAMs to use = 0
-TODO: Total RAMs use when put 0 bits in match overhead: 97
-TODO: Total RAMs use when put 0 bits in match overhead: 97
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 8 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 16 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 24 bits in match overhead
-~~~~~~~~~~~~~~~~~~~~~
- Examining placing 32 bits in match overhead
-
-##########################################
-
-Best Ram Usage is 97 rams
-Best Immediate placement is 0 bits
##########################################
Call to decide_action_data_placement(stage=0, table=process_packet_out_table)
@@ -821,7 +699,7 @@
Allocating Action Logical Table ID 0 in stage 1
----------------------------------------------
-Call to Allocate P4 Table with table ingress_port_counter, number_entries = 510, table id = None, and match type = exact
+Call to Allocate P4 Table with table ingress_port_counter, number_entries = 512, table id = None, and match type = exact
Allocating in stage 1
----------------------------------------------
@@ -850,23 +728,185 @@
Logical Table ID in stage 1 was not supplied by table placement for table ingress_port_count_table.
Allocating Logical Table ID 0 in stage 1
Allocating Table Type ID 0 of type exact in stage 1
-Match Overhead:
- Field --version_valid-- [3:0] (4 bits)
- Field --instruction_address-- [1:0] (2 bits)
- Field --statistics_pointer-- [19:0] (20 bits)
+Too few bits (9) specified to address ingress_port_counter from table ingress_port_count_table. 10 are needed.
+The most significant 1 bit will be padded with zeros.
+----------------------------------------------
+ Call to allocate_hash_distribution_units with
+ hash_algorithm = identity
+ hash_output_width = 10
+ hash_bits_need = 10
+ output_hash_bit_start = 0
+ immediate_bit_positions = None
+ used_for = Statistics Address
+----------------------------------------------
+available_tuples_sorted_by_parity_bytes_available = [(0, 3, 0), (1, 3, 0)]
+available_tuples_split_sorted_by_parity_bytes_available = []
+Allocate fresh exact match group / hash group
+Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md.ingress_port[7:0]}.
+Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md.ingress_port[8:8]}.
+-------------------
+Call to _allocate_hash_distribution_and_hash_bits
+ p4_table = ingress_port_count_table
+ used_for = Statistics Address
+ hash_distribution_hash_id = 0
+ hash_group_id = 0
+ hash_bits_in_units = OrderedDict([(0, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9])])
+ address_left_shift = 1
+-------------------
+Allocating Hash Distribution Group 0/0 for table ingress_port_count_table in stage 1.
+Allocating Hash Bit 0 in hash match group 0 for table ingress_port_count_table in stage 1.
+Allocating Hash Bit 1 in hash match group 0 for table ingress_port_count_table in stage 1.
+Allocating Hash Bit 2 in hash match group 0 for table ingress_port_count_table in stage 1.
+Allocating Hash Bit 3 in hash match group 0 for table ingress_port_count_table in stage 1.
+Allocating Hash Bit 4 in hash match group 0 for table ingress_port_count_table in stage 1.
+Allocating Hash Bit 5 in hash match group 0 for table ingress_port_count_table in stage 1.
+Allocating Hash Bit 6 in hash match group 0 for table ingress_port_count_table in stage 1.
+Allocating Hash Bit 7 in hash match group 0 for table ingress_port_count_table in stage 1.
+Allocating Hash Bit 8 in hash match group 0 for table ingress_port_count_table in stage 1.
+Allocating Hash Bit 9 in hash match group 0 for table ingress_port_count_table in stage 1.
+seed = 0x0
+set the seed to be [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
+Hash Function 0
+hash_bit_0 = ig_intr_md.ingress_port[0] ^ 0
+hash_bit_1 = ig_intr_md.ingress_port[1] ^ 0
+hash_bit_2 = ig_intr_md.ingress_port[2] ^ 0
+hash_bit_3 = ig_intr_md.ingress_port[3] ^ 0
+hash_bit_4 = ig_intr_md.ingress_port[4] ^ 0
+hash_bit_5 = ig_intr_md.ingress_port[5] ^ 0
+hash_bit_6 = ig_intr_md.ingress_port[6] ^ 0
+hash_bit_7 = ig_intr_md.ingress_port[7] ^ 0
+hash_bit_8 = ig_intr_md.ingress_port[8] ^ 0
+hash_bit_9 = 0
+hash_bit_10 = 0
+hash_bit_11 = 0
+hash_bit_12 = 0
+hash_bit_13 = 0
+hash_bit_14 = 0
+hash_bit_15 = 0
+hash_bit_16 = 0
+hash_bit_17 = 0
+hash_bit_18 = 0
+hash_bit_19 = 0
+hash_bit_20 = 0
+hash_bit_21 = 0
+hash_bit_22 = 0
+hash_bit_23 = 0
+hash_bit_24 = 0
+hash_bit_25 = 0
+hash_bit_26 = 0
+hash_bit_27 = 0
+hash_bit_28 = 0
+hash_bit_29 = 0
+hash_bit_30 = 0
+hash_bit_31 = 0
+hash_bit_32 = 0
+hash_bit_33 = 0
+hash_bit_34 = 0
+hash_bit_35 = 0
+hash_bit_36 = 0
+hash_bit_37 = 0
+hash_bit_38 = 0
+hash_bit_39 = 0
+hash_bit_40 = 0
+hash_bit_41 = 0
+hash_bit_42 = 0
+hash_bit_43 = 0
+hash_bit_44 = 0
+hash_bit_45 = 0
+hash_bit_46 = 0
+hash_bit_47 = 0
+hash_bit_48 = 0
+hash_bit_49 = 0
+hash_bit_50 = 0
+hash_bit_51 = 0
-Logical Table ID in stage 1 was not supplied by table placement for table ingress_port_count_table.
-Allocating Logical Table ID 0 in stage 1
-Allocating Table Type ID 0 of type exact in stage 1
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
-Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
+Allocating: Byte 2 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
+Allocating: Byte 3 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
Match Table Resource Request is:
SRAM Resource Request for table ingress_port_count_table (of type match), with 0 ways wants 0 rams.
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
-Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
+Allocating: Byte 2 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
+Allocating: Byte 3 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
No micro instructions needed for action count_ingress executed from table ingress_port_count_table.
Allocating Action ALU 0 (32 bits) in stage 1 for match table ingress_port_count_table's action count_ingress
Allocating VLIW Instruction : 0 in stage 1 for match table ingress_port_count_table's action count_ingress
+My hash-action stage table is
+StageHashActionTable
+ stage_number: 1
+ number_entries 1024
+ pack_format:
+ Pack Format:
+ table_word_width: 0
+ memory_word_width: 0
+ entries_per_table_word: 0
+ number_memory_units_per_table_word: 0
+ entry_list: [
+]
+
+ p4_table: 'ingress_port_count_table'
+ stage_table_handle: 0
+ stage_table_type_handle: 0
+ stage_gateway_table: StageGatewayTable
+ stage_number: 1
+ number_entries 0
+ memory_resource_allocation GatewayMemoryResourceAllocation:
+ memory_type: gateway
+ memory_units: [[15]]
+ home_row: -1
+ stateful_action_bus_output: None
+
+ p4_table: '_condition_2'
+
+ match_group_resource_allocation:
+ vliw_resource_allocation:
+ action handle 536870914 maps to:
+VliwResourceAllocation:
+ match_table_name: ingress_port_count_table
+ p4_action: count_ingress
+ address_to_use: 1
+ full_address: 64
+ vliw_instruction_number: 0
+ color: 0
+ direction: ingress
+ micro_instructions:
+
+ action_to_vliw_mapping:
+ action handle 536870914 maps to vliw instruction 0, color 0, and direction ingress and is found in instruction address 1
+ hash_distribution_usages:
+ MAU Hash Distribution Resource Usage for P4 table ingress_port_count_table
+ exact_match_group_resource_allocation : HashMatchGroupResourceAllocation:
+ match_groups: [(0, 16)]
+ match_group_key_bit_width: 9
+ match_group_phv_bit_scrambling: OrderedDict([(('ig_intr_md.ingress_port', 0), 0), (('ig_intr_md.ingress_port', 1), 1), (('ig_intr_md.ingress_port', 2), 2), (('ig_intr_md.ingress_port', 3), 3), (('ig_intr_md.ingress_port', 4), 4), (('ig_intr_md.ingress_port', 5), 5), (('ig_intr_md.ingress_port', 6), 6), (('ig_intr_md.ingress_port', 7), 7), (('ig_intr_md.ingress_port', 8), 8)])
+ ('ig_intr_md.ingress_port', 0) -> 0
+ ('ig_intr_md.ingress_port', 1) -> 1
+ ('ig_intr_md.ingress_port', 2) -> 2
+ ('ig_intr_md.ingress_port', 3) -> 3
+ ('ig_intr_md.ingress_port', 4) -> 4
+ ('ig_intr_md.ingress_port', 5) -> 5
+ ('ig_intr_md.ingress_port', 6) -> 6
+ ('ig_intr_md.ingress_port', 7) -> 7
+ ('ig_intr_md.ingress_port', 8) -> 8
+ hash_function_dictionary: OrderedDict([(0, <p4c_tofino.target.tofino.llir.mau.stage.resources.hash_function.HashFunction object at 0x7ff9ed76bcd0>)])
+ hash_group_id: 0
+ seed: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
+ table_direction: ingress
+
+ hash_distribution_resource_allocations :
+Hash Distribution:
+ source_hash_group : 0
+ hash_distribution_hash_id : 0
+ hash_distribution_group_id : 0
+ hash_distribution_used_for : Statistics Address
+ table_direction : ingress
+ bits_to_use : [0, 1, 2, 3, 4, 5, 6, 7, 8, 9]
+ left_shift : 1
+ expanded_lo : False
+ expanded_hi : False
+ expanded_bit_width : 0
+ immediate_position : unused
+
+
+
----------------------------------------------
Call to Allocate P4 Table with table egress_port_count_table__action__, number_entries = 1024, table id = None, and match type = exact
@@ -906,7 +946,7 @@
Allocating Action Logical Table ID 1 in stage 1
----------------------------------------------
-Call to Allocate P4 Table with table egress_port_counter, number_entries = 510, table id = None, and match type = exact
+Call to Allocate P4 Table with table egress_port_counter, number_entries = 512, table id = None, and match type = exact
Allocating in stage 1
----------------------------------------------
@@ -926,8 +966,8 @@
ram_word_select_bits : 0
ram_enable_select_bits : 0
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
-Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
+Allocating: Byte 2 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
+Allocating: Byte 3 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
----------------------------------------------
Call to Allocate P4 Table with table egress_port_count_table, number_entries = 1024, table id = None, and match type = exact
@@ -937,22 +977,185 @@
Logical Table ID in stage 1 was not supplied by table placement for table egress_port_count_table.
Allocating Logical Table ID 1 in stage 1
Allocating Table Type ID 1 of type exact in stage 1
-Match Overhead:
- Field --version_valid-- [3:0] (4 bits)
- Field --statistics_pointer-- [19:0] (20 bits)
+Too few bits (9) specified to address egress_port_counter from table egress_port_count_table. 10 are needed.
+The most significant 1 bit will be padded with zeros.
+----------------------------------------------
+ Call to allocate_hash_distribution_units with
+ hash_algorithm = identity
+ hash_output_width = 10
+ hash_bits_need = 10
+ output_hash_bit_start = 0
+ immediate_bit_positions = None
+ used_for = Statistics Address
+----------------------------------------------
+available_tuples_sorted_by_parity_bytes_available = [(1, 3, 0), (0, 2, 4)]
+available_tuples_split_sorted_by_parity_bytes_available = []
+Allocate fresh exact match group / hash group
+Allocating: Byte 8 is of type exact and member of group 0 (parity group 1) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
+Allocating: Byte 9 is of type exact and member of group 0 (parity group 1) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
+-------------------
+Call to _allocate_hash_distribution_and_hash_bits
+ p4_table = egress_port_count_table
+ used_for = Statistics Address
+ hash_distribution_hash_id = 1
+ hash_group_id = 1
+ hash_bits_in_units = OrderedDict([(0, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9])])
+ address_left_shift = 1
+-------------------
+Allocating Hash Distribution Group 1/0 for table egress_port_count_table in stage 1.
+Allocating Hash Bit 0 in hash match group 1 for table egress_port_count_table in stage 1.
+Allocating Hash Bit 1 in hash match group 1 for table egress_port_count_table in stage 1.
+Allocating Hash Bit 2 in hash match group 1 for table egress_port_count_table in stage 1.
+Allocating Hash Bit 3 in hash match group 1 for table egress_port_count_table in stage 1.
+Allocating Hash Bit 4 in hash match group 1 for table egress_port_count_table in stage 1.
+Allocating Hash Bit 5 in hash match group 1 for table egress_port_count_table in stage 1.
+Allocating Hash Bit 6 in hash match group 1 for table egress_port_count_table in stage 1.
+Allocating Hash Bit 7 in hash match group 1 for table egress_port_count_table in stage 1.
+Allocating Hash Bit 8 in hash match group 1 for table egress_port_count_table in stage 1.
+Allocating Hash Bit 9 in hash match group 1 for table egress_port_count_table in stage 1.
+seed = 0x0
+set the seed to be [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
+Hash Function 0
+hash_bit_0 = ig_intr_md_for_tm.ucast_egress_port[0] ^ 0
+hash_bit_1 = ig_intr_md_for_tm.ucast_egress_port[1] ^ 0
+hash_bit_2 = ig_intr_md_for_tm.ucast_egress_port[2] ^ 0
+hash_bit_3 = ig_intr_md_for_tm.ucast_egress_port[3] ^ 0
+hash_bit_4 = ig_intr_md_for_tm.ucast_egress_port[4] ^ 0
+hash_bit_5 = ig_intr_md_for_tm.ucast_egress_port[5] ^ 0
+hash_bit_6 = ig_intr_md_for_tm.ucast_egress_port[6] ^ 0
+hash_bit_7 = ig_intr_md_for_tm.ucast_egress_port[7] ^ 0
+hash_bit_8 = ig_intr_md_for_tm.ucast_egress_port[8] ^ 0
+hash_bit_9 = 0
+hash_bit_10 = 0
+hash_bit_11 = 0
+hash_bit_12 = 0
+hash_bit_13 = 0
+hash_bit_14 = 0
+hash_bit_15 = 0
+hash_bit_16 = 0
+hash_bit_17 = 0
+hash_bit_18 = 0
+hash_bit_19 = 0
+hash_bit_20 = 0
+hash_bit_21 = 0
+hash_bit_22 = 0
+hash_bit_23 = 0
+hash_bit_24 = 0
+hash_bit_25 = 0
+hash_bit_26 = 0
+hash_bit_27 = 0
+hash_bit_28 = 0
+hash_bit_29 = 0
+hash_bit_30 = 0
+hash_bit_31 = 0
+hash_bit_32 = 0
+hash_bit_33 = 0
+hash_bit_34 = 0
+hash_bit_35 = 0
+hash_bit_36 = 0
+hash_bit_37 = 0
+hash_bit_38 = 0
+hash_bit_39 = 0
+hash_bit_40 = 0
+hash_bit_41 = 0
+hash_bit_42 = 0
+hash_bit_43 = 0
+hash_bit_44 = 0
+hash_bit_45 = 0
+hash_bit_46 = 0
+hash_bit_47 = 0
+hash_bit_48 = 0
+hash_bit_49 = 0
+hash_bit_50 = 0
+hash_bit_51 = 0
-Logical Table ID in stage 1 was not supplied by table placement for table egress_port_count_table.
-Allocating Logical Table ID 1 in stage 1
-Allocating Table Type ID 1 of type exact in stage 1
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
-Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
+Allocating: Byte 2 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
+Allocating: Byte 3 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
Match Table Resource Request is:
SRAM Resource Request for table egress_port_count_table (of type match), with 0 ways wants 0 rams.
-Allocating: Byte 0 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
-Allocating: Byte 1 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
+Allocating: Byte 2 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {ig_intr_md_for_tm.ucast_egress_port[7:0]}.
+Allocating: Byte 3 is of type exact and member of group 0 (parity group 0) with 16 bytes. for {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]}.
No micro instructions needed for action count_egress executed from table egress_port_count_table.
Allocating Action ALU 0 (32 bits) in stage 1 for match table egress_port_count_table's action count_egress
Allocating VLIW Instruction : 0 in stage 1 for match table egress_port_count_table's action count_egress
+My hash-action stage table is
+StageHashActionTable
+ stage_number: 1
+ number_entries 1024
+ pack_format:
+ Pack Format:
+ table_word_width: 0
+ memory_word_width: 0
+ entries_per_table_word: 0
+ number_memory_units_per_table_word: 0
+ entry_list: [
+]
+
+ p4_table: 'egress_port_count_table'
+ stage_table_handle: 1
+ stage_table_type_handle: 1
+ stage_gateway_table: StageGatewayTable
+ stage_number: 1
+ number_entries 0
+ memory_resource_allocation GatewayMemoryResourceAllocation:
+ memory_type: gateway
+ memory_units: [[14]]
+ home_row: -1
+ stateful_action_bus_output: None
+
+ p4_table: 'egress_port_count_table_always_true_condition'
+
+ match_group_resource_allocation:
+ vliw_resource_allocation:
+ action handle 536870916 maps to:
+VliwResourceAllocation:
+ match_table_name: egress_port_count_table
+ p4_action: count_egress
+ address_to_use: 0
+ full_address: 64
+ vliw_instruction_number: 0
+ color: 0
+ direction: ingress
+ micro_instructions:
+
+ action_to_vliw_mapping:
+ action handle 536870916 maps to vliw instruction 0, color 0, and direction ingress and is found in instruction address 0
+ hash_distribution_usages:
+ MAU Hash Distribution Resource Usage for P4 table egress_port_count_table
+ exact_match_group_resource_allocation : HashMatchGroupResourceAllocation:
+ match_groups: [(0, 16)]
+ match_group_key_bit_width: 73
+ match_group_phv_bit_scrambling: OrderedDict([(('ig_intr_md_for_tm.ucast_egress_port', 0), 64), (('ig_intr_md_for_tm.ucast_egress_port', 1), 65), (('ig_intr_md_for_tm.ucast_egress_port', 2), 66), (('ig_intr_md_for_tm.ucast_egress_port', 3), 67), (('ig_intr_md_for_tm.ucast_egress_port', 4), 68), (('ig_intr_md_for_tm.ucast_egress_port', 5), 69), (('ig_intr_md_for_tm.ucast_egress_port', 6), 70), (('ig_intr_md_for_tm.ucast_egress_port', 7), 71), (('ig_intr_md_for_tm.ucast_egress_port', 8), 72)])
+ ('ig_intr_md_for_tm.ucast_egress_port', 0) -> 64
+ ('ig_intr_md_for_tm.ucast_egress_port', 1) -> 65
+ ('ig_intr_md_for_tm.ucast_egress_port', 2) -> 66
+ ('ig_intr_md_for_tm.ucast_egress_port', 3) -> 67
+ ('ig_intr_md_for_tm.ucast_egress_port', 4) -> 68
+ ('ig_intr_md_for_tm.ucast_egress_port', 5) -> 69
+ ('ig_intr_md_for_tm.ucast_egress_port', 6) -> 70
+ ('ig_intr_md_for_tm.ucast_egress_port', 7) -> 71
+ ('ig_intr_md_for_tm.ucast_egress_port', 8) -> 72
+ hash_function_dictionary: OrderedDict([(0, <p4c_tofino.target.tofino.llir.mau.stage.resources.hash_function.HashFunction object at 0x7ff9ed752590>)])
+ hash_group_id: 1
+ seed: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
+ table_direction: ingress
+
+ hash_distribution_resource_allocations :
+Hash Distribution:
+ source_hash_group : 1
+ hash_distribution_hash_id : 1
+ hash_distribution_group_id : 0
+ hash_distribution_used_for : Statistics Address
+ table_direction : ingress
+ bits_to_use : [0, 1, 2, 3, 4, 5, 6, 7, 8, 9]
+ left_shift : 1
+ expanded_lo : False
+ expanded_hi : False
+ expanded_bit_width : 0
+ immediate_position : unused
+
+
+
Cannot find table object for 'process_packet_out_table_always_true_condition'.
Cannot find table object for 'egress_port_count_table_always_true_condition'.
Cannot find table object for 'process_packet_out_table_always_true_condition'.
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.resources.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.resources.log
index 8fd4959..7ee6b09 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.resources.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.resources.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: mau.resources.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Fri Sep 8 08:24:30 2017 |
+| Created on: Wed Sep 13 00:58:56 2017 |
+---------------------------------------------------------------------+
@@ -9,7 +9,7 @@
| Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID |
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| 0 | 1 | 16 | 1 | 0 | 2 | 3 | 3 | 3 | 3 | 0 | 1 | 0 | 4 | 0 | 2 | 1 | 2 |
-| 1 | 2 | 0 | 9 | 0 | 2 | 4 | 4 | 0 | 1 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2 |
+| 1 | 6 | 0 | 29 | 2 | 2 | 4 | 4 | 0 | 1 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2 |
| 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
@@ -21,7 +21,7 @@
| 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| | | | | | | | | | | | | | | | | | |
-| Totals | 3 | 16 | 10 | 0 | 4 | 7 | 7 | 3 | 4 | 0 | 3 | 0 | 4 | 0 | 2 | 1 | 4 |
+| Totals | 7 | 16 | 30 | 2 | 4 | 7 | 7 | 3 | 4 | 0 | 3 | 0 | 4 | 0 | 2 | 1 | 4 |
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@@ -29,7 +29,7 @@
| Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| 0 | 0.78% | 24.24% | 0.24% | 0.00% | 12.50% | 3.75% | 6.25% | 12.50% | 9.38% | 0.00% | 25.00% | 0.00% | 3.12% | 0.00% | 6.25% | 3.12% | 12.50% |
-| 1 | 1.56% | 0.00% | 2.16% | 0.00% | 12.50% | 5.00% | 8.33% | 0.00% | 3.12% | 0.00% | 50.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 12.50% |
+| 1 | 4.69% | 0.00% | 6.97% | 33.33% | 12.50% | 5.00% | 8.33% | 0.00% | 3.12% | 0.00% | 50.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 12.50% |
| 2 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
| 3 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
| 4 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
@@ -41,7 +41,7 @@
| 10 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
| 11 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% |
| | | | | | | | | | | | | | | | | | |
-| Average | 0.20% | 2.02% | 0.20% | 0.00% | 2.08% | 0.73% | 1.22% | 1.04% | 1.04% | 0.00% | 6.25% | 0.00% | 0.26% | 0.00% | 0.52% | 0.26% | 2.08% |
+| Average | 0.46% | 2.02% | 0.60% | 2.78% | 2.08% | 0.73% | 1.22% | 1.04% | 1.04% | 0.00% | 6.25% | 0.00% | 0.26% | 0.00% | 0.52% | 0.26% | 2.08% |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@@ -60,9 +60,9 @@
| table0_counter | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 |
| _condition_2 | 1 | 2 | 9 | 1 | 0 | 0 | 0 | 0 | 0 |
| ingress_port_count_table__action__ | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
-| ingress_port_count_table | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
+| ingress_port_count_table | 1 | 2 | 10 | 0 | 0 | 0 | 0 | 0 | 1 |
| egress_port_count_table__action__ | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
-| egress_port_count_table | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
+| egress_port_count_table | 1 | 2 | 10 | 1 | 0 | 0 | 0 | 0 | 1 |
| ingress_port_counter | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 |
| egress_port_counter | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 |
--------------------------------------------------------------------------------------------------------------------
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.rf.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.rf.log
index 6c57767..4f65b6b 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.rf.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.rf.log
@@ -1,6 +1,6 @@
+---------------------------------------------------------------------+
| Log file: mau.rf.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Fri Sep 8 08:24:30 2017 |
+| Created on: Wed Sep 13 00:58:56 2017 |
+---------------------------------------------------------------------+
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.sram.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.sram.log
index cac1c83..606da50 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.sram.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.sram.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: mau.sram.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Fri Sep 8 08:24:30 2017 |
+| Created on: Wed Sep 13 00:58:56 2017 |
+---------------------------------------------------------------------+
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.tcam.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.tcam.log
index 355fc95..221e0cf 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.tcam.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.tcam.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: mau.tcam.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Fri Sep 8 08:24:30 2017 |
+| Created on: Wed Sep 13 00:58:56 2017 |
+---------------------------------------------------------------------+
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.tp.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.tp.log
index 44131b9..069309e 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.tp.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/mau.tp.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: mau.tp.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Fri Sep 8 08:24:30 2017 |
+| Created on: Wed Sep 13 00:58:56 2017 |
+---------------------------------------------------------------------+
----- Stage 0 ------
@@ -31,10 +31,10 @@
------------------------------------------
Running Table Placement 4
------------------------------------------
-Cannot use hash action for table ingress_port_count_table.
-Cannot use hash-action for table ingress_port_count_table with no key because the number of entries required by side-effect table ingress_port_counter is not a power of 2 -- 510.
-Cannot use hash action for table egress_port_count_table.
-Cannot use hash-action for table egress_port_count_table with no key because the number of entries required by side-effect table egress_port_counter is not a power of 2 -- 510.
+Can use hash action for table ingress_port_count_table??? True
+Decided that match table ingress_port_count_table is more efficiently allocated using hash-action to ingress_port_counter.
+Can use hash action for table egress_port_count_table??? True
+Decided that match table egress_port_count_table is more efficiently allocated using hash-action to egress_port_counter.
Cannot use hash action for table process_packet_out_table.
Table process_packet_out_table has no side effect tables.
Cannot use hash action for table table0.
@@ -42,8 +42,8 @@
------------------------------------------
Table Groups
------------------------------------------
-Table Grouping (ingress) with match table ingress_port_count_table (1024) [ingress_port_count_table__action__ (1024), ingress_port_counter (510)]
-Table Grouping (ingress) with match table egress_port_count_table (1024) [egress_port_count_table__action__ (1024), egress_port_counter (510)]
+Table Grouping (ingress) with match table ingress_port_count_table (1024) [ingress_port_count_table__action__ (1024), ingress_port_counter (512)]
+Table Grouping (ingress) with match table egress_port_count_table (1024) [egress_port_count_table__action__ (1024), egress_port_counter (512)]
Table Grouping (ingress) with match table process_packet_out_table (1024) [process_packet_out_table__action__ (1024)]
Table Grouping (ingress) with match table table0 (512) [table0__action__ (512), table0_counter (512)]
Table Grouping (ingress) with condition table _condition_0 (0) []
@@ -81,13 +81,13 @@
Nodes could place:
_condition_2 (4)
->> choose Table Grouping (ingress) with match table ingress_port_count_table (1024) [ingress_port_count_table__action__ (1024), ingress_port_counter (510)]
+>> choose Table Grouping (ingress) with match table ingress_port_count_table (1024) [ingress_port_count_table__action__ (1024), ingress_port_counter (512)]
Earliest stage can place: 1
Placing table: ingress_port_count_table__action__ with 1024 entries
-Placing table: ingress_port_counter with 510 entries
+Placing table: ingress_port_counter with 512 entries
Table ingress_port_count_table__action__ with 0 entries is directly referenced
Table ingress_port_counter with 4096 entries is indirectly referenced
-Match Table ingress_port_count_table has a total of 1 entries in stage 1
+Match Table ingress_port_count_table has a total of 1024 entries in stage 1
Direct mapped table ingress_port_count_table__action__ has 0 entries
>> set ingress_port_count_table (5) to placed
>> set _condition_2 (4) to placed
@@ -96,15 +96,15 @@
egress_port_count_table (6)
egress_port_count_table and _condition_2 not mutually exclusive
egress_port_count_table and ingress_port_count_table not mutually exclusive
->> choose Table Grouping (ingress) with match table egress_port_count_table (1024) [egress_port_count_table__action__ (1024), egress_port_counter (510)]
+>> choose Table Grouping (ingress) with match table egress_port_count_table (1024) [egress_port_count_table__action__ (1024), egress_port_counter (512)]
Earliest stage can place: 1
egress_port_count_table and _condition_2 not mutually exclusive
egress_port_count_table and ingress_port_count_table not mutually exclusive
Placing table: egress_port_count_table__action__ with 1024 entries
-Placing table: egress_port_counter with 510 entries
+Placing table: egress_port_counter with 512 entries
Table egress_port_count_table__action__ with 0 entries is directly referenced
Table egress_port_counter with 4096 entries is indirectly referenced
-Match Table egress_port_count_table has a total of 1 entries in stage 1
+Match Table egress_port_count_table has a total of 1024 entries in stage 1
Direct mapped table egress_port_count_table__action__ has 0 entries
>> set egress_port_count_table (6) to placed
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/pa.characterize.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/pa.characterize.log
index fbedb72..e6b17ae 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/pa.characterize.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/pa.characterize.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: pa.characterize.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Fri Sep 8 08:24:30 2017 |
+| Created on: Wed Sep 13 00:58:56 2017 |
+---------------------------------------------------------------------+
Program: default
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/pa.constraints.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/pa.constraints.log
index 0813a74..dabf298 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/pa.constraints.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/pa.constraints.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: pa.constraints.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Fri Sep 8 08:24:30 2017 |
+| Created on: Wed Sep 13 00:58:56 2017 |
+---------------------------------------------------------------------+
To populate this log file, include --print-pa-constraints as a compiler argument.
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/pa.liveness.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/pa.liveness.log
index 35be00a..b01c3da 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/pa.liveness.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/pa.liveness.log
@@ -1,6 +1,6 @@
+---------------------------------------------------------------------+
| Log file: pa.liveness.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Fri Sep 8 08:24:30 2017 |
+| Created on: Wed Sep 13 00:58:56 2017 |
+---------------------------------------------------------------------+
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/pa.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/pa.log
index 0311aff..c36f6b92 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/pa.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/pa.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: pa.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Fri Sep 8 08:24:30 2017 |
+| Created on: Wed Sep 13 00:58:56 2017 |
+---------------------------------------------------------------------+
HLIR Version: 0.10.5
@@ -549,7 +549,7 @@
parse_pkt_in and parse_pkt_out are exclusive parse states
parse_tcp and parse_udp are exclusive parse states
->>Event 'pa_init' at time 1504859072.87
+>>Event 'pa_init' at time 1505264338.44
Took 0.01 seconds
--------------------------------------------
PHV MAU Groups: 90
@@ -827,7 +827,7 @@
eg_intr_md.egress_cos <3 bits egress parsed imeta>
->>Event 'pa_resv' at time 1504859072.88
+>>Event 'pa_resv' at time 1505264338.44
Took 0.00 seconds
-----------------------------------------------
@@ -869,7 +869,7 @@
Group 2 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv32
Group 3 32 bits -- avail 16 -- ingress avail 16 and remain 15 and promised 1 and req 1 -- egress avail 16 and remain 12 and promised 0 and req 0 -- as if deparsed True -- container_to_use phv48
Reserving 32-bit container for ingress: phv0
->>Event 'pa_bridge' at time 1504859072.91
+>>Event 'pa_bridge' at time 1505264338.48
Took 0.04 seconds
-----------------------------------------------
@@ -922,7 +922,7 @@
| Overall total | 1 (0.30%) | 32 (0.52%) | 6144 |
---------------------------------------------------------------------------
->>Event 'pa_phase0' at time 1504859072.92
+>>Event 'pa_phase0' at time 1505264338.48
Took 0.00 seconds
-----------------------------------------------
@@ -975,7 +975,7 @@
| Overall total | 1 (0.30%) | 32 (0.52%) | 6144 |
---------------------------------------------------------------------------
->>Event 'pa_critical' at time 1504859072.92
+>>Event 'pa_critical' at time 1505264338.49
Took 0.00 seconds
-----------------------------------------------
@@ -2023,8 +2023,8 @@
| Overall total | 52 (15.48%) | 968 (15.76%) | 6144 |
-----------------------------------------------------------------------------
->>Event 'pa_overlay' at time 1504859082.02
- Took 9.10 seconds
+>>Event 'pa_overlay' at time 1505264347.52
+ Took 9.03 seconds
-----------------------------------------------
Allocating remaining parsed fields
@@ -2288,8 +2288,8 @@
| Overall total | 0 (0.00%) | 0 (0.00%) | 6144 |
--------------------------------------------------------------------------
->>Event 'pa_meta1' at time 1504859082.54
- Took 0.52 seconds
+>>Event 'pa_meta1' at time 1505264348.03
+ Took 0.51 seconds
-----------------------------------------------
Allocating metadata (pass 1)
@@ -2433,7 +2433,7 @@
--------------------------------------------------------------------------
Sorted metadata field instances to allocate: 0 / 0 bits (0 ingress bits and 0 egress bits)
->>Event 'pa_pov' at time 1504859082.61
+>>Event 'pa_pov' at time 1505264348.10
Took 0.07 seconds
-----------------------------------------------
@@ -2590,7 +2590,7 @@
egress
phv81 (8 bits)
>> 8 total bits
->>Event 'pa_meta2' at time 1504859082.73
+>>Event 'pa_meta2' at time 1505264348.22
Took 0.12 seconds
-----------------------------------------------
@@ -2733,7 +2733,7 @@
final start_bit = 5
(1) msb_offset = 8
***Allocating phv67[7:5] for ig_intr_md_for_tm.drop_ctl[2:0]
->>Event 'pa_meta_init' at time 1504859082.80
+>>Event 'pa_meta_init' at time 1505264348.28
Took 0.06 seconds
-----------------------------------------------
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/pa.results.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/pa.results.log
index 2e8758a..ca2c03f 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/pa.results.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/pa.results.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: pa.results.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Fri Sep 8 08:24:30 2017 |
+| Created on: Wed Sep 13 00:58:56 2017 |
+---------------------------------------------------------------------+
Program: default
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/parde.calcfields.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/parde.calcfields.log
index 4ee6b6a..5e040e1 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/parde.calcfields.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/parde.calcfields.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: parde.calcfields.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Fri Sep 8 08:24:30 2017 |
+| Created on: Wed Sep 13 00:58:56 2017 |
+---------------------------------------------------------------------+
Reserving 0 16-bit ingress tphvs for residual checksums
@@ -19,19 +19,19 @@
Number of reachable states from state <POV initialization>_<Ingress intrinsic metadata>_<Phase 0> : 10
Number of reachable states from state <Shim start state> : 11
parser_state_calculations:[
- parse_tcp_140004581269072
- parse_tcp_140004588184656
- parse_udp_140004588183696
- parse_ipv4_140004588185488
- parse_ethernet_140004582443984
- parse_pkt_in_140004588185680
- parse_pkt_out_140004588358736
- default_parser_140004588358928
- start_140004588186320
- <Phase 0>_140004583263632
- <Ingress intrinsic metadata>_140004583263312
- <POV initialization>_140004583264016
- <Shim start state>_140004583329936
+ parse_tcp_140711407463824
+ parse_tcp_140711409960016
+ parse_udp_140711409959056
+ parse_ipv4_140711409960848
+ parse_ethernet_140711405223056
+ parse_pkt_in_140711409961040
+ parse_pkt_out_140711409828752
+ default_parser_140711409828560
+ start_140711409961680
+ <Phase 0>_140711400881488
+ <Ingress intrinsic metadata>_140711400881168
+ <POV initialization>_140711400881872
+ <Shim start state>_140711400968272
]
parser_calculations: [
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/parde.config.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/parde.config.log
index d59725b..faca781 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/parde.config.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/parde.config.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: parde.config.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Fri Sep 8 08:24:30 2017 |
+| Created on: Wed Sep 13 00:58:56 2017 |
+---------------------------------------------------------------------+
Configuring deparser.inp.iim.ii_phv_csum.csum_cfg[0].csum_cfg_entry[0].zero_m_s_b = 1
@@ -16399,5 +16399,5 @@
[None]
---------------
Deparse order:
-Ingress: ['metadata_bridge', '_bridged_intr_md_', 'packet_in_hdr', 'packet_out_hdr', 'ethernet', 'ipv4', 'udp', 'tcp']
-Egress: ['packet_in_hdr', 'packet_out_hdr', 'ethernet', 'ipv4', 'udp', 'tcp']
+Ingress: ['metadata_bridge', '_bridged_intr_md_', 'packet_out_hdr', 'packet_in_hdr', 'ethernet', 'ipv4', 'udp', 'tcp']
+Egress: ['packet_out_hdr', 'packet_in_hdr', 'ethernet', 'ipv4', 'udp', 'tcp']
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/parde.error.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/parde.error.log
index cf3dfaa..8d9e1e5 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/parde.error.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/parde.error.log
@@ -1,6 +1,6 @@
+---------------------------------------------------------------------+
| Log file: parde.error.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Fri Sep 8 08:24:30 2017 |
+| Created on: Wed Sep 13 00:58:56 2017 |
+---------------------------------------------------------------------+
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/parde.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/parde.log
index f0bc0fc..e7c0177 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/parde.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/parde.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: parde.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Fri Sep 8 08:24:30 2017 |
+| Created on: Wed Sep 13 00:58:56 2017 |
+---------------------------------------------------------------------+
># Begin digest init (pre-PHV)
@@ -18,14 +18,14 @@
># Begin unroll of HLIR parse graph
>## Create shadow parse graph and find loops
>## Entrypoint 'p4_parse_state.start'
-Creating shadow state: 'p4_parse_state.start' -> 'shadow_state (start, 140004582444624)'
-Creating shadow state: 'p4_parse_state.parse_pkt_in' -> 'shadow_state (parse_pkt_in, 140004582444432)'
-Creating shadow state: 'p4_parse_state.parse_ethernet' -> 'shadow_state (parse_ethernet, 140004582443856)'
-Creating shadow state: 'p4_parse_state.parse_ipv4' -> 'shadow_state (parse_ipv4, 140004582443728)'
-Creating shadow state: 'p4_parse_state.parse_tcp' -> 'shadow_state (parse_tcp, 140004582443600)'
-Creating shadow state: 'p4_parse_state.parse_udp' -> 'shadow_state (parse_udp, 140004582443664)'
-Creating shadow state: 'p4_parse_state.default_parser' -> 'shadow_state (default_parser, 140004582443536)'
-Creating shadow state: 'p4_parse_state.parse_pkt_out' -> 'shadow_state (parse_pkt_out, 140004582443344)'
+Creating shadow state: 'p4_parse_state.start' -> 'shadow_state (start, 140711405223504)'
+Creating shadow state: 'p4_parse_state.parse_pkt_in' -> 'shadow_state (parse_pkt_in, 140711405223312)'
+Creating shadow state: 'p4_parse_state.parse_ethernet' -> 'shadow_state (parse_ethernet, 140711405222736)'
+Creating shadow state: 'p4_parse_state.parse_ipv4' -> 'shadow_state (parse_ipv4, 140711405222608)'
+Creating shadow state: 'p4_parse_state.parse_tcp' -> 'shadow_state (parse_tcp, 140711405222480)'
+Creating shadow state: 'p4_parse_state.parse_udp' -> 'shadow_state (parse_udp, 140711405222544)'
+Creating shadow state: 'p4_parse_state.default_parser' -> 'shadow_state (default_parser, 140711405222416)'
+Creating shadow state: 'p4_parse_state.parse_pkt_out' -> 'shadow_state (parse_pkt_out, 140711405222352)'
># End unroll of HLIR parse graph
># Begin deparser init
>## Create records for gress 0
@@ -43,8 +43,8 @@
Created record for 'p4_header_instance.tcp'
Created record for 'p4_header_instance.udp'
>## Build record ordering for gress 0
->## Build field ordering for record 'packet_in_hdr'
>## Build field ordering for record 'packet_out_hdr'
+>## Build field ordering for record 'packet_in_hdr'
>## Build field ordering for record 'ethernet'
>## Build field ordering for record 'ipv4'
>## Build field ordering for record 'udp'
@@ -64,8 +64,8 @@
Created record for 'p4_header_instance.tcp'
Created record for 'p4_header_instance.udp'
>## Build record ordering for gress 1
->## Build field ordering for record 'packet_in_hdr'
>## Build field ordering for record 'packet_out_hdr'
+>## Build field ordering for record 'packet_in_hdr'
>## Build field ordering for record 'ethernet'
>## Build field ordering for record 'ipv4'
>## Build field ordering for record 'udp'
@@ -89,13 +89,13 @@
># Begin scraping deparser POV allocation from raw PHV allocation
PHV layout: [0, 0, 0, 0, 66, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None]
>## Scraping individual POV records
-POV 33 -> packet_out_hdr
-POV 34 -> ethernet
POV 35 -> ipv4
POV 36 -> tcp
POV 37 -> udp
-POV 38 -> pov_bmeta
POV 32 -> packet_in_hdr
+POV 38 -> pov_bmeta
+POV 33 -> packet_out_hdr
+POV 34 -> ethernet
>## Setting up array bits
># End scraping deparser POV allocation from raw PHV allocation
># Begin parser POV rewrite
@@ -116,12 +116,12 @@
># Begin scraping deparser POV allocation from raw PHV allocation
PHV layout: [81, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None]
>## Scraping individual POV records
-POV 1 -> packet_out_hdr
-POV 2 -> ethernet
POV 3 -> ipv4
POV 4 -> tcp
POV 5 -> udp
POV 0 -> packet_in_hdr
+POV 1 -> packet_out_hdr
+POV 2 -> ethernet
>## Setting up array bits
># End scraping deparser POV allocation from raw PHV allocation
># Begin parser POV rewrite
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/parser.characterize.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/parser.characterize.log
index 4d4e6e3..7542705 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/parser.characterize.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/parser.characterize.log
@@ -1,6 +1,6 @@
+---------------------------------------------------------------------+
| Log file: parser.characterize.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Fri Sep 8 08:24:30 2017 |
+| Created on: Wed Sep 13 00:58:56 2017 |
+---------------------------------------------------------------------+
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/transform.log b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/transform.log
index 6f53712..d589e9a 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/transform.log
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/logs/transform.log
@@ -1,7 +1,7 @@
+---------------------------------------------------------------------+
| Log file: transform.log |
| Compiler version: 5.1.0 (fca32d1) |
-| Created on: Fri Sep 8 08:24:30 2017 |
+| Created on: Wed Sep 13 00:58:56 2017 |
+---------------------------------------------------------------------+
-------------------------------
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/tofino.bin b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/tofino.bin
index a11fd1e..ab65327 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/tofino.bin
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/tofino.bin
Binary files differ
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/deparser.html b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/deparser.html
index 3cd0e6e..54c0e30 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/deparser.html
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/deparser.html
@@ -163,7 +163,7 @@
<tr class="fde_row_0">
- <td style="border-right: 1px solid black">packet_in_hdr (32)</td>
+ <td style="border-right: 1px solid black">packet_out_hdr (33)</td>
<td>129</td>
<td>129</td>
<td>-</td>
@@ -172,7 +172,7 @@
<tr class="fde_row_1">
- <td style="border-right: 1px solid black">packet_out_hdr (33)</td>
+ <td style="border-right: 1px solid black">packet_in_hdr (32)</td>
<td>129</td>
<td>129</td>
<td>-</td>
@@ -400,7 +400,7 @@
<tr><td><center>POV</center></td><td colspan=4><center>PHV</center></td></tr>
<tr class="fde_row_0">
- <td style="border-right: 1px solid black">packet_in_hdr (0)</td>
+ <td style="border-right: 1px solid black">packet_out_hdr (1)</td>
<td><font color=#333333><i>340</i></font></td>
<td><font color=#333333><i>340</i></font></td>
<td>-</td>
@@ -409,7 +409,7 @@
<tr class="fde_row_1">
- <td style="border-right: 1px solid black">packet_out_hdr (1)</td>
+ <td style="border-right: 1px solid black">packet_in_hdr (0)</td>
<td><font color=#333333><i>340</i></font></td>
<td><font color=#333333><i>340</i></font></td>
<td>-</td>
@@ -569,7 +569,7 @@
</div></div><br><br>
</td></tr>
</table>
-<br><i>Created on Fri Sep 8 08:24:46 2017</i>
+<br><i>Created on Wed Sep 13 00:59:12 2017</i>
<br><i>Compiler version: 5.1.0 (fca32d1)</i>
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/mau.html b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/mau.html
index 3adfa0d..ba6c17f 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/mau.html
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/mau.html
@@ -49,10 +49,10 @@
</tr>
<tr>
<td align="center">1</td>
+<td align="center">6</td>
+<td align="center">0</td>
+<td align="center">29</td>
<td align="center">2</td>
-<td align="center">0</td>
-<td align="center">9</td>
-<td align="center">0</td>
<td align="center">2</td>
<td align="center">4</td>
<td align="center">4</td>
@@ -289,10 +289,10 @@
</tr>
<tr>
<td align="center">Totals</td>
-<td align="center">3</td>
+<td align="center">7</td>
<td align="center">16</td>
-<td align="center">10</td>
-<td align="center">0</td>
+<td align="center">30</td>
+<td align="center">2</td>
<td align="center">4</td>
<td align="center">7</td>
<td align="center">7</td>
@@ -352,10 +352,10 @@
</tr>
<tr>
<td align="center">1</td>
-<td align="center" bgcolor="#07fe00" >1.56%</td>
+<td align="center" bgcolor="#17fe00" >4.69%</td>
<td align="center" bgcolor="#00c000" >0.00%</td>
-<td align="center" bgcolor="#0bfe00" >2.16%</td>
-<td align="center" bgcolor="#00c000" >0.00%</td>
+<td align="center" bgcolor="#23fe00" >6.97%</td>
+<td align="center" bgcolor="#a9fe00" >33.33%</td>
<td align="center" bgcolor="#3ffe00" >12.50%</td>
<td align="center" bgcolor="#19fe00" >5.00%</td>
<td align="center" bgcolor="#2afe00" >8.33%</td>
@@ -592,10 +592,10 @@
</tr>
<tr>
<td align="center">Average</td>
-<td align="center" bgcolor="#01fe00" >0.20%</td>
+<td align="center" bgcolor="#02fe00" >0.46%</td>
<td align="center" bgcolor="#0afe00" >2.02%</td>
-<td align="center" bgcolor="#01fe00" >0.20%</td>
-<td align="center" bgcolor="#00c000" >0.00%</td>
+<td align="center" bgcolor="#03fe00" >0.60%</td>
+<td align="center" bgcolor="#0efe00" >2.78%</td>
<td align="center" bgcolor="#0afe00" >2.08%</td>
<td align="center" bgcolor="#03fe00" >0.73%</td>
<td align="center" bgcolor="#06fe00" >1.22%</td>
@@ -3409,20 +3409,32 @@
<text x="18" y="22" textLength="30" lengthAdjust="spacingAndGlyphs" textHeight="6" heightAdjust="spacingAndGlyphs" style="fill:black;">Crossbar</text>
<rect x="16" y="32" width="8" height="8" style="stroke:black; stroke-width:1; fill:chartreuse""><title>Crossbar Byte 0 in exact Group 0 (parity group 0)
contains:
- {ig_intr_md_for_tm.ucast_egress_port[7:0]} for table _condition_2
+ {ig_intr_md.ingress_port[7:0]} for table ingress_port_count_table
</title></rect>
<rect x="16" y="40" width="8" height="8" style="stroke:black; stroke-width:1; fill:chartreuse""><title>Crossbar Byte 1 in exact Group 0 (parity group 0)
contains:
+ {unused[6:0], ig_intr_md.ingress_port[8:8]} for table ingress_port_count_table
+</title></rect>
+<rect x="16" y="48" width="8" height="8" style="stroke:black; stroke-width:1; fill:chartreuse""><title>Crossbar Byte 2 in exact Group 0 (parity group 0)
+contains:
+ {ig_intr_md_for_tm.ucast_egress_port[7:0]} for table _condition_2
+</title></rect>
+<rect x="16" y="56" width="8" height="8" style="stroke:black; stroke-width:1; fill:chartreuse""><title>Crossbar Byte 3 in exact Group 0 (parity group 0)
+contains:
{unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]} for table _condition_2
</title></rect>
-<rect x="16" y="48" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Crossbar Byte 2 in exact Group 0 (parity group 0)</title></rect>
-<rect x="16" y="56" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Crossbar Byte 3 in exact Group 0 (parity group 0)</title></rect>
<rect x="24" y="32" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Crossbar Byte 4 in exact Group 0 (parity group 0)</title></rect>
<rect x="24" y="40" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Crossbar Byte 5 in exact Group 0 (parity group 0)</title></rect>
<rect x="24" y="48" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Crossbar Byte 6 in exact Group 0 (parity group 0)</title></rect>
<rect x="24" y="56" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Crossbar Byte 7 in exact Group 0 (parity group 0)</title></rect>
-<rect x="40" y="32" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Crossbar Byte 8 in exact Group 0 (parity group 1)</title></rect>
-<rect x="40" y="40" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Crossbar Byte 9 in exact Group 0 (parity group 1)</title></rect>
+<rect x="40" y="32" width="8" height="8" style="stroke:black; stroke-width:1; fill:chocolate""><title>Crossbar Byte 8 in exact Group 0 (parity group 1)
+contains:
+ {ig_intr_md_for_tm.ucast_egress_port[7:0]} for table egress_port_count_table
+</title></rect>
+<rect x="40" y="40" width="8" height="8" style="stroke:black; stroke-width:1; fill:chocolate""><title>Crossbar Byte 9 in exact Group 0 (parity group 1)
+contains:
+ {unused[6:0], ig_intr_md_for_tm.ucast_egress_port[8:8]} for table egress_port_count_table
+</title></rect>
<rect x="40" y="48" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Crossbar Byte 10 in exact Group 0 (parity group 1)</title></rect>
<rect x="40" y="56" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Crossbar Byte 11 in exact Group 0 (parity group 1)</title></rect>
<rect x="48" y="32" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Crossbar Byte 12 in exact Group 0 (parity group 1)</title></rect>
@@ -3789,7 +3801,7 @@
Unit Number: 42
Entry Bit Width: 128
Depth: 1024</title></rect>
-<rect x="360" y="104" width="16" height="16" style="stroke:black; stroke-width:1; fill:chocolate""><title>SRAM:
+<rect x="360" y="104" width="16" height="16" style="stroke:black; stroke-width:1; fill:coral""><title>SRAM:
Row: 4 Col: 6
Unit Number: 54
Entry Bit Width: 128
@@ -3822,7 +3834,7 @@
Unit Number: 66
Entry Bit Width: 128
Depth: 1024</title></rect>
-<rect x="360" y="56" width="16" height="16" style="stroke:black; stroke-width:1; fill:coral""><title>SRAM:
+<rect x="360" y="56" width="16" height="16" style="stroke:black; stroke-width:1; fill:cornflowerblue""><title>SRAM:
Row: 6 Col: 6
Unit Number: 78
Entry Bit Width: 128
@@ -3875,7 +3887,7 @@
Unit Number: 43
Entry Bit Width: 128
Depth: 1024</title></rect>
-<rect x="384" y="104" width="16" height="16" style="stroke:black; stroke-width:1; fill:chocolate""><title>SRAM:
+<rect x="384" y="104" width="16" height="16" style="stroke:black; stroke-width:1; fill:coral""><title>SRAM:
Row: 4 Col: 7
Unit Number: 55
Entry Bit Width: 128
@@ -3908,7 +3920,7 @@
Unit Number: 67
Entry Bit Width: 128
Depth: 1024</title></rect>
-<rect x="384" y="56" width="16" height="16" style="stroke:black; stroke-width:1; fill:coral""><title>SRAM:
+<rect x="384" y="56" width="16" height="16" style="stroke:black; stroke-width:1; fill:cornflowerblue""><title>SRAM:
Row: 6 Col: 7
Unit Number: 79
Entry Bit Width: 128
@@ -4247,9 +4259,12 @@
Result Bit width: 1
Depth: 512</title></rect>
<text x="82" y="254" textLength="46" lengthAdjust="spacingAndGlyphs" textHeight="6" heightAdjust="spacingAndGlyphs" style="fill:black;">Hash Distr.</text>
-<rect x="80" y="264" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Distribution Group:
+<rect x="80" y="264" width="8" height="8" style="stroke:black; stroke-width:1; fill:chartreuse""><title>Hash Distribution Group:
Hash ID: 0
Group ID: 0
+
+ Occupied By:
+ingress_port_count_table
</title></rect>
<rect x="88" y="264" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Distribution Group:
Hash ID: 0
@@ -4259,9 +4274,12 @@
Hash ID: 0
Group ID: 2
</title></rect>
-<rect x="104" y="264" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Distribution Group:
+<rect x="104" y="264" width="8" height="8" style="stroke:black; stroke-width:1; fill:chocolate""><title>Hash Distribution Group:
Hash ID: 1
Group ID: 0
+
+ Occupied By:
+egress_port_count_table
</title></rect>
<rect x="112" y="264" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Distribution Group:
Hash ID: 1
@@ -4272,16 +4290,26 @@
Group ID: 2
</title></rect>
<text x="170" y="238" textLength="46" lengthAdjust="spacingAndGlyphs" textHeight="6" heightAdjust="spacingAndGlyphs" style="fill:black;">Hash Bits</text>
-<rect x="176" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 0 in hash match group 0</title></rect>
-<rect x="184" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 1 in hash match group 0</title></rect>
-<rect x="192" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 2 in hash match group 0</title></rect>
-<rect x="200" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 3 in hash match group 0</title></rect>
-<rect x="208" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 4 in hash match group 0</title></rect>
-<rect x="216" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 5 in hash match group 0</title></rect>
-<rect x="224" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 6 in hash match group 0</title></rect>
-<rect x="232" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 7 in hash match group 0</title></rect>
-<rect x="240" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 8 in hash match group 0</title></rect>
-<rect x="248" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 9 in hash match group 0</title></rect>
+<rect x="176" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:chartreuse""><title>Hash Bit 0 in hash match group 0
+Occupied by: ingress_port_count_table for Statistics Address</title></rect>
+<rect x="184" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:chartreuse""><title>Hash Bit 1 in hash match group 0
+Occupied by: ingress_port_count_table for Statistics Address</title></rect>
+<rect x="192" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:chartreuse""><title>Hash Bit 2 in hash match group 0
+Occupied by: ingress_port_count_table for Statistics Address</title></rect>
+<rect x="200" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:chartreuse""><title>Hash Bit 3 in hash match group 0
+Occupied by: ingress_port_count_table for Statistics Address</title></rect>
+<rect x="208" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:chartreuse""><title>Hash Bit 4 in hash match group 0
+Occupied by: ingress_port_count_table for Statistics Address</title></rect>
+<rect x="216" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:chartreuse""><title>Hash Bit 5 in hash match group 0
+Occupied by: ingress_port_count_table for Statistics Address</title></rect>
+<rect x="224" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:chartreuse""><title>Hash Bit 6 in hash match group 0
+Occupied by: ingress_port_count_table for Statistics Address</title></rect>
+<rect x="232" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:chartreuse""><title>Hash Bit 7 in hash match group 0
+Occupied by: ingress_port_count_table for Statistics Address</title></rect>
+<rect x="240" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:chartreuse""><title>Hash Bit 8 in hash match group 0
+Occupied by: ingress_port_count_table for Statistics Address</title></rect>
+<rect x="248" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:chartreuse""><title>Hash Bit 9 in hash match group 0
+Occupied by: ingress_port_count_table for Statistics Address</title></rect>
<rect x="256" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 10 in hash match group 0</title></rect>
<rect x="264" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 11 in hash match group 0</title></rect>
<rect x="272" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 12 in hash match group 0</title></rect>
@@ -4333,16 +4361,26 @@
<rect x="256" y="272" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 49 in hash match group 0</title></rect>
<rect x="264" y="272" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 50 in hash match group 0</title></rect>
<rect x="272" y="272" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 51 in hash match group 0</title></rect>
-<rect x="296" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 0 in hash match group 1</title></rect>
-<rect x="304" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 1 in hash match group 1</title></rect>
-<rect x="312" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 2 in hash match group 1</title></rect>
-<rect x="320" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 3 in hash match group 1</title></rect>
-<rect x="328" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 4 in hash match group 1</title></rect>
-<rect x="336" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 5 in hash match group 1</title></rect>
-<rect x="344" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 6 in hash match group 1</title></rect>
-<rect x="352" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 7 in hash match group 1</title></rect>
-<rect x="360" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 8 in hash match group 1</title></rect>
-<rect x="368" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 9 in hash match group 1</title></rect>
+<rect x="296" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:chocolate""><title>Hash Bit 0 in hash match group 1
+Occupied by: egress_port_count_table for Statistics Address</title></rect>
+<rect x="304" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:chocolate""><title>Hash Bit 1 in hash match group 1
+Occupied by: egress_port_count_table for Statistics Address</title></rect>
+<rect x="312" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:chocolate""><title>Hash Bit 2 in hash match group 1
+Occupied by: egress_port_count_table for Statistics Address</title></rect>
+<rect x="320" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:chocolate""><title>Hash Bit 3 in hash match group 1
+Occupied by: egress_port_count_table for Statistics Address</title></rect>
+<rect x="328" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:chocolate""><title>Hash Bit 4 in hash match group 1
+Occupied by: egress_port_count_table for Statistics Address</title></rect>
+<rect x="336" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:chocolate""><title>Hash Bit 5 in hash match group 1
+Occupied by: egress_port_count_table for Statistics Address</title></rect>
+<rect x="344" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:chocolate""><title>Hash Bit 6 in hash match group 1
+Occupied by: egress_port_count_table for Statistics Address</title></rect>
+<rect x="352" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:chocolate""><title>Hash Bit 7 in hash match group 1
+Occupied by: egress_port_count_table for Statistics Address</title></rect>
+<rect x="360" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:chocolate""><title>Hash Bit 8 in hash match group 1
+Occupied by: egress_port_count_table for Statistics Address</title></rect>
+<rect x="368" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:chocolate""><title>Hash Bit 9 in hash match group 1
+Occupied by: egress_port_count_table for Statistics Address</title></rect>
<rect x="376" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 10 in hash match group 1</title></rect>
<rect x="384" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 11 in hash match group 1</title></rect>
<rect x="392" y="248" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>Hash Bit 12 in hash match group 1</title></rect>
@@ -4754,7 +4792,7 @@
Unit: 13
Entry Bit Width: 44
Depth: 4</title></rect>
-<rect x="72" y="40" width="8" height="8" style="stroke:black; stroke-width:1; fill:cornflowerblue""><title>Gateway Table Gateway:
+<rect x="72" y="40" width="8" height="8" style="stroke:black; stroke-width:1; fill:crimson""><title>Gateway Table Gateway:
Unit: 14
Entry Bit Width: 44
Depth: 4
@@ -4966,7 +5004,7 @@
Unit Number: 23
Entry Bit Width: 11
Depth: 1024</title></rect>
-<rect x="280" y="104" width="8" height="8" style="stroke:black; stroke-width:1; fill:chocolate""><title>Map RAM:
+<rect x="280" y="104" width="8" height="8" style="stroke:black; stroke-width:1; fill:coral""><title>Map RAM:
Row: 4 Unit: 0
Unit Number: 24
Entry Bit Width: 11
@@ -4974,7 +5012,7 @@
Occupied By: ingress_port_counter
Used For: synthetic two port
</title></rect>
-<rect x="288" y="104" width="8" height="8" style="stroke:black; stroke-width:1; fill:chocolate""><title>Map RAM:
+<rect x="288" y="104" width="8" height="8" style="stroke:black; stroke-width:1; fill:coral""><title>Map RAM:
Row: 4 Unit: 1
Unit Number: 25
Entry Bit Width: 11
@@ -5032,7 +5070,7 @@
Unit Number: 35
Entry Bit Width: 11
Depth: 1024</title></rect>
-<rect x="280" y="56" width="8" height="8" style="stroke:black; stroke-width:1; fill:coral""><title>Map RAM:
+<rect x="280" y="56" width="8" height="8" style="stroke:black; stroke-width:1; fill:cornflowerblue""><title>Map RAM:
Row: 6 Unit: 0
Unit Number: 36
Entry Bit Width: 11
@@ -5040,7 +5078,7 @@
Occupied By: egress_port_counter
Used For: synthetic two port
</title></rect>
-<rect x="288" y="56" width="8" height="8" style="stroke:black; stroke-width:1; fill:coral""><title>Map RAM:
+<rect x="288" y="56" width="8" height="8" style="stroke:black; stroke-width:1; fill:cornflowerblue""><title>Map RAM:
Row: 6 Unit: 1
Unit Number: 37
Entry Bit Width: 11
@@ -5103,10 +5141,10 @@
Unit: 0 right</title></rect>
<rect x="336" y="152" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>128-bit Statistics ALU:
Unit: 2 right</title></rect>
-<rect x="336" y="104" width="8" height="8" style="stroke:black; stroke-width:1; fill:chocolate""><title>128-bit Statistics ALU:
+<rect x="336" y="104" width="8" height="8" style="stroke:black; stroke-width:1; fill:coral""><title>128-bit Statistics ALU:
Unit: 4 right
Occupied By: ingress_port_counter</title></rect>
-<rect x="336" y="56" width="8" height="8" style="stroke:black; stroke-width:1; fill:coral""><title>128-bit Statistics ALU:
+<rect x="336" y="56" width="8" height="8" style="stroke:black; stroke-width:1; fill:cornflowerblue""><title>128-bit Statistics ALU:
Unit: 6 right
Occupied By: egress_port_counter</title></rect>
<rect x="336" y="176" width="8" height="8" style="stroke:black; stroke-width:1; fill:white""><title>128-bit Meter ALU:
@@ -5578,7 +5616,7 @@
ID: 0
Occupied By: ingress_port_count_table</title></rect>
-<rect x="192" y="600" width="8" height="8" style="stroke:black; stroke-width:1; fill:crimson""><title>Logical Table ID:
+<rect x="192" y="600" width="8" height="8" style="stroke:black; stroke-width:1; fill:chocolate""><title>Logical Table ID:
ID: 1
Occupied By: egress_port_count_table</title></rect>
@@ -5625,7 +5663,7 @@
ID: 15
</title></rect>
<text x="562" y="22" textLength="94" lengthAdjust="spacingAndGlyphs" textHeight="6" heightAdjust="spacingAndGlyphs" style="fill:black;">PHV Container Activity</text>
-<rect x="560" y="48" width="8" height="8" style="stroke:black; stroke-width:1; fill:crimson""><title>32-bit ALU:
+<rect x="560" y="48" width="8" height="8" style="stroke:black; stroke-width:1; fill:chocolate""><title>32-bit ALU:
Unit: 0
Occupied By:
For Match Table ingress_port_count_table's action count_ingress:
@@ -6084,13 +6122,13 @@
<text x="610" y="38" textLength="14" lengthAdjust="spacingAndGlyphs" textHeight="6" heightAdjust="spacingAndGlyphs" style="fill:black;">16</text>
<text x="650" y="38" textLength="14" lengthAdjust="spacingAndGlyphs" textHeight="6" heightAdjust="spacingAndGlyphs" style="fill:black;">8</text>
<text x="722" y="54" style="fill:black; font-weight:bold;">Legend</text>
-<rect x="720" y="64" width="16" height="16" style="stroke:black; stroke-width:1; fill:crimson""><title>egress_port_count_table</title></rect>
+<rect x="720" y="64" width="16" height="16" style="stroke:black; stroke-width:1; fill:chocolate""><title>egress_port_count_table</title></rect>
<text x="738" y="78" style="fill:black;">egress_port_count_table</text>
-<rect x="720" y="88" width="16" height="16" style="stroke:black; stroke-width:1; fill:coral""><title>egress_port_counter</title></rect>
+<rect x="720" y="88" width="16" height="16" style="stroke:black; stroke-width:1; fill:cornflowerblue""><title>egress_port_counter</title></rect>
<text x="738" y="102" style="fill:black;">egress_port_counter</text>
<rect x="720" y="112" width="16" height="16" style="stroke:black; stroke-width:1; fill:chartreuse""><title>ingress_port_count_table</title></rect>
<text x="738" y="126" style="fill:black;">ingress_port_count_table</text>
-<rect x="720" y="136" width="16" height="16" style="stroke:black; stroke-width:1; fill:chocolate""><title>ingress_port_counter</title></rect>
+<rect x="720" y="136" width="16" height="16" style="stroke:black; stroke-width:1; fill:coral""><title>ingress_port_counter</title></rect>
<text x="738" y="150" style="fill:black;">ingress_port_counter</text>
<rect x="720" y="168" width="16" height="16" style="stroke:black; stroke-width:1; fill:gray""><title>Unavailable</title></rect>
@@ -6101,13 +6139,13 @@
<rect x="712" y="32" width="224" height="168" style="stroke:black; stroke-width:1; fill:none""></rect>
<text x="978" y="54" style="fill:black;">Totals</text>
<text x="986" y="78" style="fill:black;">Exact Match Input xbar</text>
-<text x="994" y="102" style="fill:black;"> 2 of 128 (1.56%)</text>
+<text x="994" y="102" style="fill:black;"> 6 of 128 (4.69%)</text>
<text x="986" y="126" style="fill:black;">Ternary Match Input xbar</text>
<text x="994" y="150" style="fill:black;"> 0 of 66 (0.00%)</text>
<text x="986" y="174" style="fill:black;">Hash Bit</text>
-<text x="994" y="198" style="fill:black;"> 9 of 416 (2.16%)</text>
+<text x="994" y="198" style="fill:black;"> 29 of 416 (6.97%)</text>
<text x="986" y="222" style="fill:black;">Hash Dist Unit</text>
-<text x="994" y="246" style="fill:black;"> 0 of 6 (0.00%)</text>
+<text x="994" y="246" style="fill:black;"> 2 of 6 (33.33%)</text>
<text x="986" y="270" style="fill:black;">Gateway</text>
<text x="994" y="294" style="fill:black;"> 2 of 16 (12.50%)</text>
<text x="986" y="318" style="fill:black;">SRAM</text>
@@ -31964,7 +32002,7 @@
</svg><br>
-<br><i>Created on Fri Sep 8 08:24:43 2017</i>
+<br><i>Created on Wed Sep 13 00:59:09 2017</i>
<br><i>Compiler version: 5.1.0 (fca32d1)</i>
</div>
</body>
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/parser.egress.html b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/parser.egress.html
index b086e4f..5db9132 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/parser.egress.html
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/parser.egress.html
@@ -6639,7 +6639,7 @@
<br></td></tr>
</table>
-<br><i>Created on Fri Sep 8 08:24:46 2017</i>
+<br><i>Created on Wed Sep 13 00:59:12 2017</i>
<br><i>Compiler version: 5.1.0 (fca32d1)</i>
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/parser.ingress.html b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/parser.ingress.html
index 892950e..79553ab 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/parser.ingress.html
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/parser.ingress.html
@@ -7420,7 +7420,7 @@
<br></td></tr>
</table>
-<br><i>Created on Fri Sep 8 08:24:46 2017</i>
+<br><i>Created on Wed Sep 13 00:59:12 2017</i>
<br><i>Compiler version: 5.1.0 (fca32d1)</i>
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/phv_allocation.html b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/phv_allocation.html
index 579b829..5998f62 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/phv_allocation.html
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/phv_allocation.html
@@ -3648,6 +3648,8 @@
ig_intr_md._pad3[2:0] in container bits [11:9]
ig_intr_md.ingress_port[8:0] in container bits [8:0]
+Field ig_intr_md.ingress_port read by table ingress_port_count_table for Statistics Address.
+Field unused read by table ingress_port_count_table for Statistics Address.
Field ig_intr_md.ingress_port read by table ingress_port_count_table's action count_ingress
</title></rect>
<text x="371" y="25" textLength="11" lengthAdjust="spacingAndGlyphs" textHeight="11" heightAdjust="spacingAndGlyphs" style="fill:black;">R<title>PHV Group: 8
@@ -3661,6 +3663,8 @@
ig_intr_md._pad3[2:0] in container bits [11:9]
ig_intr_md.ingress_port[8:0] in container bits [8:0]
+Field ig_intr_md.ingress_port read by table ingress_port_count_table for Statistics Address.
+Field unused read by table ingress_port_count_table for Statistics Address.
Field ig_intr_md.ingress_port read by table ingress_port_count_table's action count_ingress
</title></text>
<rect x="369" y="27" width="18" height="18" style="stroke:black; stroke-width:1; fill:darkseagreen""><title>PHV Group: 8
@@ -3682,6 +3686,8 @@
ig_intr_md_for_tm.ucast_egress_port[8:0] in container bits [8:0]
Field ig_intr_md_for_tm.ucast_egress_port read by table ingress_port_count_table for a gateway expression
+Field ig_intr_md_for_tm.ucast_egress_port read by table egress_port_count_table for Statistics Address.
+Field unused read by table egress_port_count_table for Statistics Address.
Field ig_intr_md_for_tm.ucast_egress_port read by table egress_port_count_table's action count_egress
</title></rect>
<text x="371" y="61" textLength="11" lengthAdjust="spacingAndGlyphs" textHeight="11" heightAdjust="spacingAndGlyphs" style="fill:black;">R<title>PHV Group: 8
@@ -3692,6 +3698,8 @@
ig_intr_md_for_tm.ucast_egress_port[8:0] in container bits [8:0]
Field ig_intr_md_for_tm.ucast_egress_port read by table ingress_port_count_table for a gateway expression
+Field ig_intr_md_for_tm.ucast_egress_port read by table egress_port_count_table for Statistics Address.
+Field unused read by table egress_port_count_table for Statistics Address.
Field ig_intr_md_for_tm.ucast_egress_port read by table egress_port_count_table's action count_egress
</title></text>
<rect x="369" y="63" width="18" height="18" style="stroke:black; stroke-width:1; fill:limegreen""><title>PHV Group: 8
@@ -31204,7 +31212,7 @@
<text x="1010" y="178" textLength="16" lengthAdjust="spacingAndGlyphs" textHeight="16" heightAdjust="spacingAndGlyphs" style="fill:black;">16</text>
<rect x="0" y="0" width="1053" height="198" style="stroke:black; stroke-width:2; fill:none""></rect>
</svg><br>
-<br><i>Created on Fri Sep 8 08:24:44 2017</i>
+<br><i>Created on Wed Sep 13 00:59:09 2017</i>
<br><i>Compiler version: 5.1.0 (fca32d1)</i>
</body>
</html>
\ No newline at end of file
diff --git a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/table_placement.html b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/table_placement.html
index eb8ba85..d754d6b 100644
--- a/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/table_placement.html
+++ b/tools/test/p4src/p4-14/p4c-out/tofino/default/montara/visualization/table_placement.html
@@ -110,10 +110,10 @@
<rect x="91" y="195" width="13" height="13" style="stroke:black; stroke-width:1; fill:white""><title>TCAM</title></rect>
<rect x="0" y="26" width="104" height="182" style="stroke:black; stroke-width:2; fill:none""></rect>
<text x="41" y="245" textLength="24" lengthAdjust="spacingAndGlyphs" textHeight="24" heightAdjust="spacingAndGlyphs" style="fill:black;">0</text>
-<rect x="117" y="26" width="13" height="13" style="stroke:black; stroke-width:1; fill:chocolate""><title>SRAM for ingress_port_counter</title></rect>
-<rect x="130" y="26" width="13" height="13" style="stroke:black; stroke-width:1; fill:chocolate""><title>SRAM for ingress_port_counter</title></rect>
-<rect x="143" y="26" width="13" height="13" style="stroke:black; stroke-width:1; fill:coral""><title>SRAM for egress_port_counter</title></rect>
-<rect x="156" y="26" width="13" height="13" style="stroke:black; stroke-width:1; fill:coral""><title>SRAM for egress_port_counter</title></rect>
+<rect x="117" y="26" width="13" height="13" style="stroke:black; stroke-width:1; fill:coral""><title>SRAM for ingress_port_counter</title></rect>
+<rect x="130" y="26" width="13" height="13" style="stroke:black; stroke-width:1; fill:coral""><title>SRAM for ingress_port_counter</title></rect>
+<rect x="143" y="26" width="13" height="13" style="stroke:black; stroke-width:1; fill:cornflowerblue""><title>SRAM for egress_port_counter</title></rect>
+<rect x="156" y="26" width="13" height="13" style="stroke:black; stroke-width:1; fill:cornflowerblue""><title>SRAM for egress_port_counter</title></rect>
<rect x="169" y="26" width="13" height="13" style="stroke:black; stroke-width:1; fill:white""><title>SRAM</title></rect>
<rect x="182" y="26" width="13" height="13" style="stroke:black; stroke-width:1; fill:white""><title>SRAM</title></rect>
<rect x="195" y="26" width="13" height="13" style="stroke:black; stroke-width:1; fill:white""><title>SRAM</title></rect>
@@ -1277,9 +1277,9 @@
<rect x="585" y="260" width="104" height="182" style="stroke:black; stroke-width:2; fill:none""></rect>
<text x="626" y="479" textLength="24" lengthAdjust="spacingAndGlyphs" textHeight="24" heightAdjust="spacingAndGlyphs" style="fill:black;">11</text>
<text x="834" y="89" style="fill:black; font-weight:bold;">Legend</text>
-<rect x="832" y="104" width="26" height="26" style="stroke:black; stroke-width:1; fill:coral""><title>egress_port_counter</title></rect>
+<rect x="832" y="104" width="26" height="26" style="stroke:black; stroke-width:1; fill:cornflowerblue""><title>egress_port_counter</title></rect>
<text x="860" y="128" style="fill:black;">egress_port_counter</text>
-<rect x="832" y="143" width="26" height="26" style="stroke:black; stroke-width:1; fill:chocolate""><title>ingress_port_counter</title></rect>
+<rect x="832" y="143" width="26" height="26" style="stroke:black; stroke-width:1; fill:coral""><title>ingress_port_counter</title></rect>
<text x="860" y="167" style="fill:black;">ingress_port_counter</text>
<rect x="832" y="182" width="26" height="26" style="stroke:black; stroke-width:1; fill:aquamarine""><title>table0</title></rect>
<text x="860" y="206" style="fill:black;">table0</text>
@@ -1401,8 +1401,8 @@
<tr>
<td align="center">ingress_port_count_table</td>
<td align="center">1</td>
-<td align="center">0</td>
-<td align="center">0</td>
+<td align="center">2</td>
+<td align="center">10</td>
<td align="center">0</td>
<td align="center">0</td>
<td align="center">0</td>
@@ -1425,8 +1425,8 @@
<tr>
<td align="center">egress_port_count_table</td>
<td align="center">1</td>
-<td align="center">0</td>
-<td align="center">0</td>
+<td align="center">2</td>
+<td align="center">10</td>
<td align="center">1</td>
<td align="center">0</td>
<td align="center">0</td>
@@ -1459,7 +1459,7 @@
<td align="center">0</td>
</tr>
</table>
-<br><i>Created on Fri Sep 8 08:24:43 2017</i>
+<br><i>Created on Wed Sep 13 00:59:09 2017</i>
<br><i>Compiler version: 5.1.0 (fca32d1)</i>
</body>
</html>
\ No newline at end of file